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參數(shù)資料
| 型號(hào)： | AFE1224E |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| 中文描述： | 2Mbps的，單對模擬前端 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大小： | 137K |
| 代理商： | AFE1224E |
6
AFE1224
THEORY OF OPERATION
The AFE1224 consists of a transmit and a receive channel.
It interfaces to the HDSL DSP through a six wire serial
interface, three wires for the transmit channel and three
wires for the receive channel. It interfaces to the HDSL
telephone line transformer and external compromise hybrid
through transmit and receive analog connections.
The transmit channel consists of a digital-to-analog con-
verter and a switched-capacitor pulse forming network fol-
lowed by a differential line driver. The pulse forming net-
work receives 2-bit digital symbol data and generates a
filtered 2B1Q analog output waveform. The differential line
driver uses a composite output stage combining class B
operation (for high efficiency driving large signals) with
class AB operation (to minimize crossover distortion).
The receive channel is designed around a fourth-order delta
sigma A/D converter. It includes a difference amplifier
designed to be used with an external compromise hybrid for
first order analog echo cancellation. A programmable gain
amplifier with gains of 0dB to +12dB is also included. The
delta-sigma modulator operating at a 24x oversampling ratio
produces a 14-bit output at rates up to 584kHz (1.168Mbps).
The receive channel operates by summing the two differen-
tial inputs, one from the line (rxLINE) and the other from the
FIGURE 2. Transmit Timing Diagram.
compromise hybrid (rxHYB). The connection of these two
inputs so that the hybrid signal is subtracted from the line
signal is described in the paragraph titled “Echo Cancella-
tion in the AFE.” The equivalent gain for each input in the
difference amp is one. The resulting signal then passes to a
programmable gain amplifier which can be set for gains of
0dB through +12dB. Following the PGA, the ADC converts
the signal to a 14-bit digital word.
The serial interface consists of three wires for transmit and
three wires for receive. The three-wire transmit interface is
transmit baud rate clock, transmit 48x oversampling clock
and Data Out. The three-wire receive interface is receive
baud rate clock, receive 48x oversampling clock and Data
In. The transmit and receive clocks are supplied to the
AFE1224 from the DSP and are completely independent.
DIGITAL DATA INTERFACE
Data is received by the AFE1224 from the DSP on the Data
In line. Data is transmitted from the AFE1224 to the DSP on
the Data Out line. The paragraphs below describe the timing
of these signals and data structure.
Data is transmitted and received in synchronization with the
48x transmit and receive clocks (tx48xCLK and rx48xCLK).
There are 48-bit times in each baud period. Data In is
FIGURE 1. DSP Interface.
HDSL
DSP
AFE1224
rxbaudCLK
rx48xCLK
Data Out
txbaudCLK
tx48xCLK
Data In
Data In
from DSP
tx48xCLK
from DSP
txbaudCLK
from DSP
2.5ns
MSB
Bit 15
48
1
2
3
4
15
16
47
48
1
LSB
Bit 0
MSB
Bit 15
2.5ns
2.5ns
2.5ns
A
B
Transmit Timing Notes: (1) A baud period consists of 48 periods of the tx48xCLK. (2) The falling edge of the txbaudCLK
can occur anywhere in area A. The rising edge can occur anywhere in area B. However, neither edge of the txbaudCLK
can occur within 4ns (on either side) of any rising edge of tx48xCLK. (3) The AFE1224 reads Data In on the rising edge
of the tx48xCLK. Data In must be stable at least 4ns before the rising edge of tx48xCLK and it must remain stable at
least 4ns after the rising edge of tx48CLK. (4) Symbol data is transferred to the transmit pulse former after the LSB is
read. The output analog symbol data reaches the peak of the symbol approximately 24 tx48xCLK periods later.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1230 | G.SHDSL ANALOG FRONT-END |
| AFE1230E | G.SHDSL ANALOG FRONT-END |
| AFE1231K | G.SHDSL ANALOG FRONT-END |
| AFE1231KG4 | G.SHDSL ANALOG FRONT-END |
| AFE2124 | Dual HDSL/SDSL ANALOG FRONT END |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1224E/1K | 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1224E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E-2/1K | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1230 | 制造商:BB 制造商全稱:BB 功能描述:G.SHDSL ANALOG FRONT-END |
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