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參數(shù)資料
| 型號： | AFE1224 |
| 英文描述： | 2Mbps, Single Pair ANALOG FRONT END |
| 中文描述： | 2Mbps的，單對模擬前端 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大小： | 137K |
| 代理商： | AFE1224 |
8
AFE1224
Loopback Control—
This bit controls the operation of
loopback. When enabled (logic 1), the rxLINE+ and rxline–
inputs are disconnected from the AFE. The rxHYB+ and
rxHYB– inputs remain connected. When disabled, the
rxLINE+ and rxLINE– inputs are connected.
Power Control—
These bits control the power dissipation
and the maximum speed of the AFE1224.
BIT
DESCRIPTION
BIT STATE
OUTPUT STATE
15 (MSB)
tx Enable Signal
0
1
AFE transmits a 0 Symbol
AFE transmits HDSL Symbol
as defined by bits 14 and 13
14 and 13
tx Symbol
Definition
00
–3 transmit symbol
01
11
10
–1 transmit symbol
+1 transmit symbol
+3 transmit symbol
12 - 10
rx Gain Settings
000
001
010
011
100
101
110
111
rx gain in AFE 0dB
rx gain in AFE 3dB
rx gain in AFE 6dB
rx gain in AFE 9dB
rx gain in AFE 12dB
rx gain in AFE reserved
rx gain in AFE reserved
rx gain in AFE reserved
9
Loopback Control
1
0
Go to loopback mode
Normal Operation
8
Not Used
N/A
7-6
Power Control
00
01
10
11
Low speed, low power
Medium Speed, power
Normal Speed, power
Normal Speed, power
5-0
Spare
N/A
TABLE I. Data Input Format.
rxbaudCLK:
This is the receive data baud rate (symbol
clock), generated by the DSP. It is 392kHz for T1 or 584kHz
for E1. It can vary from 32kHz (64kbps) to 584kHz
(1.168Mbps).
rx48xCLK:
This is the A/D converter over-sampling clock,
generated by the DSP. It is 48x the receive symbol rate or
28.032MHz for 584kHz symbol rate. This clock should run
continuously.
Data Out:
This is the 14-bit A/D converter output data (+ 2
spare bits) sent from the AFE to the DSP. The 14 bits from
the A/D Converter will be the upper bits of the 16-bit word
(bits 15-2). The spare bits (1 and 0) will be always be LOW.
Eight additional bits follow which are always HIGH. The
data is clocked out on the falling edge and valid at the rising
edge of the rx48xCLK. The bandwidth of the A/D converter
dicimation filter is equal to one-half of the symbol rate. The
nominal output rate of the A/D converter is one conversion
per symbol period. For more flexible post-processing, there
is a second true A/D conversion available in each symbol
period. In Figure 4, the first conversion is shown as Data 1
and the second conversion is shown as Data 1a. It is
recommended that rxbaudCLK be used with the rx48xCLK
to read Data 1 while Data 1a is ignored. However, either data
output may be used and both outputs may be used for more
flexible post-processing.
DATA
BITS
Data 1
16
8
16
8
48
Interdata Bits
Data 1a
Interdata bits
Total Bits/Symbol Period
DATA OUT PER SYMBOL PERIOD
FIGURE 5. Data Out Word.
ANALOG-TO-DIGITAL CONVERTER DATA
The A/D converter data from the receive channel is coded in
Binary Two’s Complement.
ANALOG INPUT
A/D CONVERTER DATA
MSB
01111111111111
00000000000000
10000000000000
LSB
Positive Full Scale
Mid Scale
Negative Full Scale
ECHO CANCELLATION IN THE AFE
The rxHYB input is subtracted from the rxLINE input for
first order echo cancellation. For correct operation, be cer-
tain that the rxLINE input is connected to the same polarity
signal at the transformer (+ to + and – to –) while the rxHYB
input is connected to opposite polarity through the compro-
mise hybrid (– to + and + to –). Refer to the basic connection
diagram in Figure 6.
SCALEABLE TIMING
The AFE1224 scales operation with the clock frequency. All
internal filters and the pulse former change frequency with
the clock speed so that the unit can be used at different
frequencies just by changing the clock speed.
For the receive channel, the digital filtering of the delta-
sigma converter scales directly with the clock speed. The
bandwidth of the converter’s decimation filter is always one-
half of the symbol rate. The only receive channel issue in
changing baud rate is the passive single pole anti-alias filter
(see the following section). For systems implementing a
broad range of speeds, selectable cut-off frequencies for the
passive anti-alias filter should be used.
MSB
LSB
14
2
A/D Converter Data
TABLE II. Data Output Format.
相關PDF資料 |
PDF描述 |
|---|---|
| AFE1224E | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| AFE1230 | G.SHDSL ANALOG FRONT-END |
| AFE1230E | G.SHDSL ANALOG FRONT-END |
| AFE1231K | G.SHDSL ANALOG FRONT-END |
| AFE1231KG4 | G.SHDSL ANALOG FRONT-END |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1224-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E | 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1224E/1K | 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應商設備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AFE1224E-1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| AFE1224E-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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