參數(shù)資料
型號(hào): AFE1224
英文描述: 2Mbps, Single Pair ANALOG FRONT END
中文描述: 2Mbps的,單對(duì)模擬前端
文件頁(yè)數(shù): 10/11頁(yè)
文件大?。?/td> 137K
代理商: AFE1224
10
AFE1224
DISCUSSION OF
SPECIFICATIONS
UNCANCELLED ECHO
A key measure of transceiver performance is uncancelled
echo. Uncancelled echo is the summation of all of the errors
in the transmit and receive paths of the AFE1224. It includes
effects of linearity, distortion and noise. Uncancelled echo is
tested in production by Burr-Brown with a circuit that is
similar to the one shown in Figure 7, Uncancelled Echo Test
Diagram.
The measurement of uncancelled echo is made as follows:
The AFE is connected to an output circuit including a typical
1:2 line transformer. The line is simulated by a 135
resistor. Symbol sequences are generated by the tester and
applied both to the AFE and to the input of an adaptive filter.
The output of the adaptive filter is subtracted from the AFE
output to form the uncancelled echo signal. Once the filter
taps have converged, the rms value of the uncancelled echo
is calculated. Since there is no far-end signal source or
additive line noise, the uncancelled echo contains only noise
and linearity errors generated in the transmit and receive
sections of the AFE1224.
The data sheet value for uncancelled echo is the ratio of
the rms uncancelled echo (referred to the receiver input
through the receiver gain) to the nominal transmitted signal
(13.5dBm into 135
, or 1.74Vrms). This echo value is
measured under a variety of conditions: with loopback
enabled (line input disconnected); with loopback disabled
under all receiver gain ranges; and with the line shorted (S
1
closed, see Figure 7).
POWER DISSIPATION
The power dissipation of the AFE1224 is digitally program-
mable by the user to three levels: normal, medium and low.
The maximum bit rate of the AFE1205 is 2.3Mbps with
normal power dissipation. At lower power dissipation lev-
els, the maximum bit rate is lower.
The power dissipation listed in the Specifications Table
applies under these normal operating conditions: 5V analog
power supply, 3.3V digital power supply, standard 13.5dBm
delivered to the line, and a pseudo-random equiprobable
sequence of HDSL output pulses. The power dissipation
specifications includes all power dissipated in the AFE1224,
but it does not include power dissipated in the external load.
MAXIMUM
SPEED
MINIMUM
SPEED
TYPICAL POWER
DISSIPATION
POWER LEVEL
Normal
Medium
Low
2.3Mbps
1.168Mbps
320kbps
64kbps
64kbps
64kbps
385mW
300mW
240mW
TABLE III. Typical Power Dissipation.
The external power is 16.5dBm: 13.5dBm to the line and
13.5dBm to the impedance matching resistors. The external
load power of 16.5dBm is 45mW. The typical power dissi-
pation in the AFE1224 under various conditions is shown in
Table III.
LAYOUT
The analog front end of an HDSL system has two conflicting
requirements. It must accept and deliver moderately high
rate digital signals and it must generate, drive, and convert
precision analog signals. To achieve optimal system perfor-
mance with the AFE1224, both the digital and the analog
sections must be treated carefully in board layout design.
The power supply for the digital section of the AFE1224 can
range from 3.3V to 5V. This supply should be decoupled to
digital ground with ceramic 0.1
μ
F capacitors placed as close
to DGND and DV
DD
as possible. One capacitor should be
placed between pins 3 and 4 and the second capacitor
between pins 11 and 12. Ideally, both a digital power supply
plane and a digital ground plane should run up to and
underneath the digital pins of the AFE1224 (pins 5 through
10). However, DV
DD
may be supplied by a wide printed
circuit board (PCB) trace. A digital ground plane underneath
all digital pins is strongly recommended.
The remaining portion of the AFE1224 should be considered
analog. All AGND pins should be connected directly to a
common analog ground plane and all AV
DD
pins should be
connected to an analog 5V power plane. Both of these planes
should have a low impedance path to the power supply. The
analog power supply pins should be decoupled to analog
ground with ceramic 0.1
μ
F capacitors placed as close to the
AFE1224 as possible. One 10
μ
F tantalum capacitor should
also be used with each AFE1224 between the analog supply
and analog ground.
Ideally, all ground planes and traces and all power planes
and traces should return to the power supply connector
before being connected together (if necessary). Each ground
and power pair should be routed over each other, should not
overlap any portion of another pair, and the pairs should be
separated by a distance of at least 0.25 inch (6mm). One
exception is that the digital and analog ground planes should
be connected together underneath the AFE1224 by a small
trace.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AFE1224-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
AFE1224E 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率(瓦特):- 電壓 - 電源,模擬:3 V ~ 3.6 V 電壓 - 電源,數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:帶卷 (TR)
AFE1224E/1K 功能描述:IC HDSL ANALOG FRONT END 28SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率(瓦特):- 電壓 - 電源,模擬:3 V ~ 3.6 V 電壓 - 電源,數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN(5x5) 包裝:帶卷 (TR)
AFE1224E-1 制造商:Rochester Electronics LLC 功能描述:- Bulk
AFE1224E-2 制造商:Rochester Electronics LLC 功能描述:- Bulk