- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄375271 > AFE1203E LJT 18C 18#20 PIN PLUG PDF資料下載
參數(shù)資料
| 型號(hào)： | AFE1203E |
| 英文描述： | LJT 18C 18#20 PIN PLUG |
| 中文描述： | 2Mbps的，單對(duì)HDSL模擬前端 |
| 文件頁(yè)數(shù)： | 6/10頁(yè) |
| 文件大小： | 193K |
| 代理商： | AFE1203E |
6
AFE1203
THEORY OF OPERATION
The transmit channel consists of a D/A converter and a
switched-capacitor pulse forming network followed by a
differential line driver. The pulse forming network receives
symbol data from the DSP and generates a 2B1Q output
waveform. The output meets the pulse mask and power
spectral density requirements defined in European Telecom-
munications Standards Institute document RTR/TM-03036
for E1 mode and in sections 6.2.1 and 6.2.2.1 of Bellcore
technical advisory TA-NWT-001210 for T1 mode. The
differential line driver uses a composite output stage com-
bining class B operation (for high efficiency driving large
signals) with class AB operation (to minimize crossover
distortion).
The receive channel is designed around a fourth-order delta
sigma A/D converter. It includes a difference amplifier
designed to be used with an external compromise hybrid for
first-order analog crosstalk reduction. A programmable gain
amplifier with gains of 0dB to +9dB is also included. The
delta sigma modulator operating at a 24X oversampling ratio
produces 14 bits of resolution at output rates up to 584kHz.
The basic functionality of the AFE1203 is illustrated in
Figure 1.
The receive channel operates by summing the two differen-
tial inputs, one from the line (rxLINE) and the other from the
compromise hybrid (rxHYB). The connection of these two
inputs so that the hybrid signal is subtracted from the line
signal is described in the paragraph titled “Echo Cancella-
tion in the AFE”. The equivalent gain for each input in the
difference amp is 1. The resulting signal then passes to a
programmable gain amplifier which can be set for gains of
0dB through 9dB. The ADC converts the signal to a
14-bit digital word, rxD13-rxD0.
SCALEABLE TIMING
The AFE1203 scales operation with the clock frequency. All
internal filters, the A/D converter, the D/A converter, and
the pulse former change frequency with the clock speed so
that the unit can be used at different frequencies by changing
the clock speed.
rxLOOP INPUT
rxLOOP is the loopback control signal. When enabled, the
rxLINE
P
and rxLINE
N
inputs are disconnected from the
AFE. The rxHYB
P
and rxHYB
N
inputs remain connected.
Loopback is enabled by applying a positive signal (Logic 1)
to rxLOOP.
ECHO CANCELLATION IN THE AFE
The rxHYB input is designed to be subtracted from the
rxLINE input for first-order echo cancellation. To accom-
plish this, note that the rxLINE input is connected to the
same polarity signal at the transformer (positive to positive
and negative to negative) while the rxHYB input is con-
nected to opposite polarity through the compromise hybrid
(negative to positive and positive to negative) as shown in
Figure 2.
RECEIVE DATA CODING
The data from the receive channel A/D converter is coded in
Straight Offset Binary.
FIGURE 1. Functional Block Diagram of AFE1203.
rxGAIN1
rxGAIN0
GAIN
0
0
1
1
0
1
0
1
0dB
3.25dB
6dB
9dB
ADC
Pulse Former
Programmable
Gain Amp
Difference
Amplifier
Differential
Line Driver
txLINE
P
txLINE
N
rxHYB
P
rxHYB
N
rxLINE
P
rxLINE
N
txDAT
rxD13 - rxD0
14
D/A
Converter
ANALOG INPUT
OUTPUT CODE (rxD13 - rxD0)
Positive Full Scale
Negative Full Scale
11111111111111
00000000000000
RECEIVE CHANNEL PROGRAMMABLE
GAIN AMPLIFIER
The gain of the amplifier at the input of the Receive Channel
is set by two gain control pins, rxGAIN1 and rxGAIN0. The
resulting gain between 0dB and +9dB is shown below.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AFE1205 | LJT 18C 18#20 PIN PLUG |
| AFE1205E | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| AFE1224 | 2Mbps, Single Pair ANALOG FRONT END |
| AFE1224E | Circular Connector; No. of Contacts:18; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:15-18 RoHS Compliant: No |
| AFE1230 | G.SHDSL ANALOG FRONT-END |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFE1203E/1K | 功能描述:電信線路管理 IC 2Mbps Sngl Pair HDSL Anlg Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1203E/1KG4 | 功能描述:電信線路管理 IC 2Mbps Sngl Pair HDSL Anlg Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1205 | 制造商:BB 制造商全稱(chēng):BB 功能描述:2Mbps, Single Pair HDSL ANALOG FRONT END |
| AFE1205E | 功能描述:電信線路管理 IC 2Mbps Sngl Pair HDSL Anlg Front End RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| AFE1205E/1K | 功能描述:IC HDSL ANALOG FRONT END 48SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。