參數(shù)資料
型號(hào): ADZS-BF537-EZLITE
廠商: Analog Devices Inc
文件頁數(shù): 49/68頁
文件大小: 0K
描述: BOARD EVAL ADSP-BF537
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
Introduction to VisualDSP++® Tools
特色產(chǎn)品: Blackfin? BF50x Series Processors
標(biāo)準(zhǔn)包裝: 1
系列: Blackfin®
類型: DSP
適用于相關(guān)產(chǎn)品: ADSP-BF537
所含物品: 評(píng)估板、軟件和說明文檔
配用: ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD
ADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE
ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN
ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR
相關(guān)產(chǎn)品: ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 53 of 68
|
February 2014
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on
Page 55 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
T1
ZO = 50
Ω (impedance)
TD = 4.04
± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
Ω
0.5pF
70
Ω
400
Ω
45
Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
Ω
Figure 51. Typical Output Delay or Hold for Driver A at VDDEXT Min
Figure 52. Typical Output Delay or Hold for Driver A at VDDEXT Max
LOAD CAPACITANCE (pF)
RISE TIME
RISE
AND
F
ALL
TIME
ns
(10
%t
o
90%)
14
12
10
8
6
4
2
0
50
100
150
200
250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
RIS
E
AND
F
ALL
TIME
ns
(10
%
to
90%)
12
10
8
6
4
2
0
50
100
150
200
250
FALL TIME
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