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參數(shù)資料
| 型號： | ADW71205YSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC RDC 12BIT W/OSC 44-LQFP |
| 標準包裝： | 1 |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 3 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-LQFP（10x10） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個差分，單極 |
AD2S1205
Rev. A | Page 14 of 20
SERIAL INTERFACE
The angular position and velocity are available on the AD2S1205
in two 12-bit registers. These registers can be accessed via a 3-wire
serial interface (SO, RD, and SCLK) that operates at clock rates
of up to 25 MHz and is compatible with SPI and DSP interface
standards. The serial interface is selected by holding the SOE pin
low. Data from the position and velocity integrators are first trans-
ferred to the position and velocity registers using the SAMPLE pin.
The RDVEL pin selects whether data is transferred from the
position or velocity register to the output register, and the CS pin
must be held low to transfer data from the selected register to the
output register. Finally, the RD input is used to read the data that
is clocked out of the output register and is available on the serial
output pin (SO). When the serial interface is selected, DB11 is used
as the serial output pin (SO), DB10 is used as the serial clock input
(SCLK), and Pin DB0 to Pin DB9 are placed into the high imped-
ance state. The timing requirements for the read cycle are described
in
.
SO Output
The output shift register is 16 bits wide. Data is clocked out of
the device as a 16-bit word by the serial clock input (SCLK).
The timing diagram for this operation is shown in Figure 8.
The 16-bit word consists of 12 bits of angular data (position or
velocity, depending on RDVEL input), one RDVEL status bit,
and three status bits (a parity bit, a degradation of signal bit, and
a loss of tracking bit). Data is clocked out MSB first from the
SO pin, beginning with DB15. DB15 through DB4 correspond
to the angular information. The angular position data format
is unsigned binary, with all 0s corresponding to 0° and all 1s cor-
responding to 360° l LSB. The angular velocity data format
is twos complement, with the MSB representing the rotation
direction. DB3 is the RDVEL status bit, with a 1 indicating
position and a 0 indicating velocity. DB2 is DOS, the degradation
of signal flag (refer to the
section). Bit 1
is LOT, the loss of tracking flag (refer to the
section). Bit 0 is PAR, the parity bit. The position and
velocity data are in odd parity format, and the data readback
always contains an odd number of logic highs (1s).
SAMPLE Input
Data is transferred from the position and velocity integrators to
the position and velocity registers, respectively, after a high-to-
low transition on the SAMPLE signal. This pin must be held low
for at least t1 to guarantee correct latching of the data. RD should
not be pulled low before this time because data will not be ready.
The converter continues to operate during the read process.
CS Input
The device is enabled when CS is held low.
RD Input
The 12-bit data bus lines are normally in a high impedance
state. The output buffer is enabled when CS and RD are held
low. The RD input is an edge-triggered input that acts as a frame
synchronization signal and an output enable. On a falling edge of
the RD signal, data is transferred to the output buffer. Data is
then available on the serial output pin (SO); however, it is only
valid after RD is held low for t9. The serial data is clocked out
of the SO pin on the rising edges of SCLK, and each data bit is
available at the SO pin on the falling edge of SCLK. However,
as the MSB is clocked out by the falling edge of RD, the MSB is
available at the SO pin on the first falling edge of SCLK. Each
subsequent bit of the data-word is shifted out on the rising edge
of SCLK and is available at the SO pin on the falling edge of
SCLK for the next 15 clock pulses.
The high-to-low transition of RD must occur during the high
time of the SCLK to avoid DB14 being shifted on the first rising
edge of the SCLK, which would result in the MSB being lost.
RD may rise high after the last falling edge of SCLK. If RD is
held low and additional SCLKs are applied after DB0 has been
read, then 0s will be clocked from the data output. When
reading data continuously, wait a minimum of t5 after RD
is released before reapplying it.
RDVEL Input
RDVEL input is used to select between the angular position
register and the angular velocity register. RDVEL is held high to
select the angular position register and low to select the angular
velocity register. The RDVEL pin must be set (stable) at least t4
before the RD pin is pulled low.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADW71205YSTZ-RL | 功能描述:R/D Converter 12 bit Parallel 44-LQFP (10x10) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):在售 類型:R/D 轉(zhuǎn)換器 分辨率（位）:12 b 采樣率（每秒）:- 數(shù)據(jù)接口:并聯(lián) 電壓源:模擬和數(shù)字 電壓 - 電源:5V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:44-LQFP 供應(yīng)商器件封裝:44-LQFP（10x10） 標準包裝:1,500 |
| ADW72909405 | 制造商:LG Corporation 功能描述:Funnel Assembly |
| ADW72909701 | 制造商:LG Corporation 功能描述:Funnel Assembly |
| ADW72909702 | 制造商:LG Corporation 功能描述:Funnel Assembly |
| ADW72909703 | 制造商:LG Corporation 功能描述:FUNNEL ASSEMBLY |
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