參數(shù)資料
型號： AD9608BCPZ-125
廠商： Analog Devices Inc
文件頁數(shù)： 1/40頁
文件大?。?/td> 0K
描述： IC ADC DUAL 10BIT 64-LFCSP
標準包裝： 1
位數(shù)： 10
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，并聯(lián)，串行，SPI
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
輸入數(shù)目和類型： 4 個單端，2 個差分
10-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V CMOS or 1.8 V LVDS output
SNR = 61.7 dBFS at 70 MHz
SFDR = 85 dBc at 70 MHz
Low power: 71 mW/channel ADC core at 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.13 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
ORA
D0A
D9A
DCOA
DRVDD
ORB
D9B
D0B
DCOB
SDIO
AGND
AVDD
SCLK
SPI
PROGRAMMING DATA
MU
X
OP
T
ION
PDWN DFS
CLK+ CLK–
MODE
CONTROLS
DCS
DUTY CYCLE
STABILIZER
SYNC
DIVIDE
1TO 8
OEB
CSB
REF
SELECT
ADC
CMO
S
/L
VD
S
OU
TPU
T
B
U
F
E
R
ADC
CMO
S
/L
VD
S
OU
TPU
T
B
U
F
E
R
AD9608
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
0997
7-
001
Figure 1.
PRODUCT HIGHLIGHTS
1.
Operates from a single 1.8 V analog power supply and
features a separate digital output driver supply to accom-
modate 1.8 V CMOS or 1.8 V LVDS logic families.
2.
Provides a patented sample-and-hold circuit that maintains
excellent performance for input frequencies up to 200 MHz
and is designed for low cost, low power, and ease of use.1
3.
Includes a standard serial port interface that supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing,
and offset adjustments.
4.
Packaged in a 64-lead, RoHS-compliant LFCSP that is pin
compatible with the AD9650, AD9269, and AD9268 16-bit
ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628
and AD9231 12-bit ADCs, and the AD9204 10-bit ADC,
enabling a simple migration path between 10-bit and 16-bit
converters sampling from 20 MSPS to 125 MSPS.
1 This product is protected by a U.S. patent.
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