
ADV7320/ADV7321
Rev. A | Page 33 of 88
Table 16. Registers 0x44 to 0x49
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset
Values
0x44
SD VSYNC-3H
0
Disabled
0x00
SD Mode
Register 3
1
VSYNC = 2.5 lines (PAL),
VSYNC = 3 lines (NTSC)
SD RTC/TR/SCR
0
Genlock disabled
0
1
Subcarrier reset
1
0
Timing reset
1
RTC enabled
SD Active Video Length
0
720 pixels
1
710 (NTSC)/702 (PAL)
SD Chroma
0
Chroma enabled
1
Chroma disabled
SD Burst
0
Enabled
1
Disabled
SD Color Bars
0
Disabled
1
Enabled
SD DAC Swap
0
DAC A = luma,
DAC B = chroma
1
DAC A = chroma,
DAC B = luma
0x45
Reserved
0x00
0x46
0
5.17 μs
0x01
SD Mode
Register 4
0
1
5.31 μs (default)
1
0
5.59 μs (must be set for
Macrovision compliance)
NTSC Color Subcarrier Adjust (Falling
Edge of HS to Start of Color Burst)
11
Reserved
0x47
SD PrPb Scale
0
Disabled
0x00
SD Mode
Register 5
1
Enabled
SD Y Scale
0
Disabled
1
Enabled
SD Hue Adjust
0
Disabled
1
Enabled
SD Brightness
0
Disabled
1
Enabled
SD Luma SSAF Gain
0
Disabled
1
Enabled
Reserved
0
0 must be written to this bit
Reserved
0
0 must be written to this bit
Reserved
0
0 must be written to this bit
0x48
Reserved
0
0x00
SD Mode
Register 6
Reserved
0
0 must be written to this bit
SD Double Buffering
0
Disabled
1
Enabled
SD Input Format
0
8-bit input
0
1
16-bit input
1
0
10-bit input
1
20-bit input
SD Digital Noise Reduction
0
Disabled
1
Enabled
SD Gamma Control
0
Disabled
1
Enabled
SD Gamma Curve
0
Gamma Curve A
1
Gamma Curve B
0x49
SD Undershoot Limiter
0
Disabled
0x00
SD Mode
Register 7
0
1
11 IRE
1
0
6 IRE
1
1.5 IRE
Reserved
0
0 must be written to this bit
SD Black Burst Output on DAC Luma
0
Disabled
1
Enabled
SD Chroma Delay
0
Disabled
0
1
4 clock cycles
1
0
8 clock cycles
1
Reserved
0
0 must be written to this bit
Reserved
0
0 must be written to this bit
1 NTSC color bar adjust should be set to 10 b for Macrovision compliance (ADV7320 only).