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參數(shù)資料
| 型號(hào)： | ADV7321KSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 21/88頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VID ENC 6-12BIT DAC'S 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻編碼器 |
| 應(yīng)用： | EVD，DVD，SD/PS/HDTV |
| 電壓 - 電源，模擬： | 2.5V |
| 電壓 - 電源，數(shù)字： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 托盤 |
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ADV7320/ADV7321
Rev. A | Page 28 of 88
Table 10. Register 0x12
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset
Values
0x12
0
0 clock cycles
0x00
HD Mode
Register 3
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
3 clock cycles
HD Y Delay with
Respect to Falling
Edge of HSYNC
1
0
4 clock cycles
0
0 clock cycles
0
1
1 clock cycle
0
1
0
2 clock cycles
0
1
3 clock cycles
HD Color Delay with
Respect to Falling
Edge of HSYNC
1
0
4 clock cycles
HD CGMS
0
Disabled
1
Enabled
HD CGMS CRC
0
Disabled
1
Enabled
Table 11. Registers 0x13 to 0x14
SR7–
SR0
Register
Bit Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register Setting
Reset
Values
0x13
HD Cr/Cb Sequence
0
Cb after falling edge of HSYNC.
0x4C
HD Mode
Register 4
1
Cr after falling edge of HSYNC.
Reserved
0
0 must be written to this bit.
HD Input Format
0
8-bit input.
1
10-bit input.
Sinc Filter on DAC D, E, F
0
Disabled.
1
Enabled.
Reserved
0
0 must be written to this bit.
HD Chroma SSAF
0
Disabled.
1
Enabled.
HD Chroma Input
0
4:4:4
1
4:2:2
HD Double Buffering
0
Disabled.
1
Enabled.
0x14
HD Mode
Register 5
HD Timing Reset
x
A low-high-low transition resets
the internal HD timing counters.
0x00
HD Hsync Generation1
0
1
HD Vsync Generation1
0
1
HD Blank Polarity
0
BLANK active high.
1
BLANK active low.
0
Macrovision disabled.
HD Macrovision for
525p and 625p
1
Macrovision enabled.
Reserved
0
0 must be written to these bits.
HD VSYNC/Field Input
0
0 = field input.
1
1 = VSYNC input.
0
Update field/line counter.
Horizontal/Vertical
Counters2
1
Field/line counter free running.
1 Used in conjunction with HD_SYNC in Register 0x02, Bit 7, set to 1.
2 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
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