
REV. 0
ADV7196A
–6–
B0
B1
B2
B3
Bxxx
Bxxx
CLOCK
PIXEL INPUT
DATA
R0
G0
R1
G1
R2
G2
G3
Rxxx
Gxxx
Rxxx
Gxxx
t
11
t
12
t
9
t
10
t
9
–
CLOCK HIGH TIME
t
10
–
CLOCK LOW TIME
t
11
–
DATA SETUP TIME
t
12
–
DATA HOLD TIME
Figure 1. 4:4:4 RGB Input Data Format Timing Diagram
CLOCK
PIXEL INPUT
DATA
Y0
Cb0
Y1
Cr0
Y2
Cb1
Cr1
Yxxx
Cbxxx
Yxxx
Crxxx
t
11
t
12
t
9
t
10
t
9
–
CLOCK HIGH TIME
t
10
–
CLOCK LOW TIME
t
11
–
DATA SETUP TIME
t
12
–
DATA HOLD TIME
Figure 2. 4:2:2 Input Data Format Timing Diagram
Cr0
Cr1
Cr2
Cr3
Crxxx
CLOCK
PIXEL INPUT
DATA
Y0
Cb0
Y1
Cb1
Y2
Cb2
Cb3
Yxxx
Cbxxx
Yxxx
Cbxxx
t
11
t
12
t
9
t
10
Crxxx
t
9
–
CLOCK HIGH TIME
t
10
–
CLOCK LOW TIME
t
11
–
DATA SETUP TIME
t
12
–
DATA HOLD TIME
Figure 3. 4:4:4 YCrCb Input Data Format Timing Diagram