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參數(shù)資料
| 型號(hào)： | ADV7196A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| 中文描述： | 多格式逐行掃描/高清晰度電視編碼器三種11位DAC，10位數(shù)據(jù)輸入，以及Macrovision |
| 文件頁(yè)數(shù)： | 29/36頁(yè) |
| 文件大?。?/td> | 501K |
| 代理商： | ADV7196A |
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REV. 0
ADV7196A
–29–
MODE REGISTER 4
MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Figure 55 shows the various operations under the control of Mode
Register 4.
MR4 BIT DESCRIPTION
Timing Reset (MR40)
Toggling MR40 from low to high and low again resets the inter-
nal horizontal and vertical timing counters
.
MODE REGISTER 5
MR5 (MR57–MR50)
(Address (SR4–SR0) = 05H)
Figure 56 shows the various operations under the control of Mode
Register 5.
MR5 BIT DESCRIPTION
Reserved (MR50)
These bit is reserved for the revision code
.
RGB Mode (MR51)
When RGB mode is enabled (MR51 = “1”) the ADV7196A accepts
unsigned binary RGB data at its input port. This control is also
available in Async Timing Mode
.
Sync on PrPb (MR52)
By default the color component output signals Pr, Pb do not contain
any horizontal sync pulses. If required they can be inserted when
MR52 = “1.” This control is not available in RGB mode
.
Color Output Swap (MR53)
By default DAC B is configured as the Pr output and DAC C as
the Pb output. In setting this bit to “1” the DAC outputs can be
swapped around so that DAC B outputs Pb and DAC C outputs
Pr. Table X demonstrates this in more detail.
Reserved (MR54–MR57)
“0” must be written to these bits.
Table X. Relationship Between Input Pixel Port, MR53
and DAC B, DAC C Outputs
In 4:4:4 Input Mod
e
Color Data
Input on Pins
Analog Output
Signal
MR53
Cr9–0
Cb/Cr9–0
Cr9–0
Cb/Cr9–0
0
0
1
1
DAC B
DAC C
DAC C
DAC
B
In 4:2:2 Input Mod
e
Color Data
Input on Pins
Analog Output
Signal
MR53
Cr9–0
Cb/Cr9–0
Cb/Cr9–0
0 or 1
0
1
Not Operational
DAC C (Pb)
DAC C (Pr)
MR47
MR42
MR44
MR46
ZERO MUST BE
WRITTEN TO
THESE BITS
MR47
–
MR41
MR45
MR43
MR41
MR40
MR40
TIMING RESET
Figure 55. Mode Register 4
MR57
MR52
MR56
MR57
–
MR54
ZERO MUST BE
WRITTEN TO
THESE BITS
MR55
MR53
MR51
MR50
MR54
MR53
0
1
DAC B = Pr
DAC C = Pr
COLOR OUTPUT
SWAP
MR52
0
1
DISABLE
ENABLE
SYNC ON PrPb
MR51
0
1
DISABLE
ENABLE
RGB MODE
RESERVED FOR
REVISION CODE
MR50
Figure 56. Mode Register 5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7196AKS | Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KST | Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7304A | Multiformat SD, Progressive Scan/HDTV Video Encoder with Six NSV 14-Bit DACs |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7196AKS | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat Progressive Scan/HDTV Encoder with Three 11-Bit DACs, 10-Bit Data Input, and Macrovision |
| ADV7197 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KS | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
| ADV7197KST | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Multiformat HDTV Encoder with Three 11-Bit DACs |
| ADV7197KSZ | 制造商:Analog Devices 功能描述:Video Encoder 3DAC 11-Bit 52-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:MULTI-FORMAT HDTV ENCODER, 3 11-BIT DACS - Bulk |
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