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參數(shù)資料
| 型號： | ADV7189KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 84/104頁 |
| 文件大?。?/td> | 890K |
| 代理商： | ADV7189KST |
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ADV7189
Table 192. Register 0x34 to 0x36
Subaddress
Register
HS Position
Control 1
Rev. A | Page 84 of 104
Bit Description
HSE[10:8]
. HS end allows the
positioning of the HS output
within the video line.
Bit
4
Comments
HS output ends
HSE[10:0] pixels
after the falling edge
of HSync.
Set to 0.
HS output starts
HSB[10:0] pixels
after the falling edge
of HSync.
Notes
Using HSB and HSE
the user can program
the position and
length of the output
HSync.
7
6
5
3
2
0
1
0
0
0
0
0
0
0
Reserved.
HSB[10:8]
. HS begin allows
the positioning of the HS
output within the video line.
Reserved.
HS Position
Control 2
0
0
0
0
0
0
0
1
0
0x34
Set to 0.
0x35
HSB[7:0]
See above, using
HSB[9:0] and HSE[9:0] the user
can program the position and
length of HS output signal.
HSE[7:0]
See above.
0
0
0
0
0
0
0
0
0x36
HS Position
Control 3
Table 193. Register 0x37
Subaddress
0x37
Register
Polarity
Bit Description
PCLK
. Sets the polarity of LLC1.
Bit
4
0
Comment
Invert polarity.
Normal polarity as per
Timing Diagrams
.
Set to 0.
Active high.
Active low.
Set to 0.
Active high.
Active low.
Set to 0.
Active high.
Active low.
7
0
1
6
0
5
0
1
3
0
1
2
0
1
0
0
0
1
Reserved.
PF
. Sets the FIELD polarity.
Reserved.
PVS
. Sets the VS polarity.
Reserved.
PHS
. Sets HS polarity.
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