參數(shù)資料
型號(hào)： ADV7189KST
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, PQFP80
封裝： LEAD FREE, MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 18/104頁(yè)
文件大?。?/td> 890K
代理商： ADV7189KST
ADV7189
Drive Strength Selection (Clock)
Rev. A | Page 18 of 104
DR_STR_C[1:0] Address 0x0E, [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the following sections:
Drive Strength Selection (Sync)
Drive Strength Selection (Data)
Table 21. DR_STR Function
DR_STR[1:0]
00
01*
10
11
*Default value.
Drive Strength Selection (Sync)
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
DR_STR_S[1:0] Address 0x0E, [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are
driven. For more information, refer to the following sections:
Drive Strength Selection (Clock)
Drive Strength Selection (Data)
Table 22. DR_STR Function
DR_STR[1:0]
00
01*
10
11
*Default value.
Description
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
Enable Subcarrier Frequency Lock Pin
EN_SFL_PIN Address 0x04, [1]
The subcarrier frequency lock pin (SDP, output only) has a
double function: it can also output raw sync-related information
(SogOut). The EN_SFL_PIN bit enables the output of
subcarrier lock information (also known as GenLock) from the
SDP core to an encoder in a decoder-encoder back-to-back
arrangement.
Table 23. EN_SFL_PIN Function
EN_SFL_PIN
Description
0*
Subcarrier frequency lock output is disabled.
1
Subcarrier frequency lock information is
presented on the SFL pin.
*Default value.
Polarity LLC Pin
PCLK Address 0x37, [0]
The polarity of the clock that leaves the ADV7189 via the LLC1
and LLC2 pins can be inverted using the PCLK bit. Note that
this inversion affects the clock for SDP.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
Note that this bit also inverts the polarity of the LLC2 clock.
Table 24. PCLK Function
PCLK
Description
0
Invert LLC output polarity.
1*
LLC output polarity normal (as per the Timing
Diagrams)
*Default value.
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