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參數(shù)資料
| 型號： | ADV7189KST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Multiformat SDTV Video Decoder |
| 中文描述： | COLOR SIGNAL DECODER, PQFP80 |
| 封裝： | LEAD FREE, MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 77/104頁 |
| 文件大小： | 890K |
| 代理商： | ADV7189KST |
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ADV7189
Table 182. Register 0x12 to 0x13
Subaddress
Register
0x12
Status Register 2
Read-only
Rev. A | Page 77 of 104
Bit Description
STATUS_2[7:0]
. Provides
information about the internal status
of the decoder.
STATUS_2[5:0].
Bit
4
Register Setting
Comments
7
6
5
3
2
1
0
x
MV color striping
detected
MV color striping
type
MV pseudosync
detected
MV AGC pulses
detected
Nonstandard line
length
Fsc frequency
nonstandard
1 = Horizontal
lock achieved
1 = Reserved bits
1 = Free Run
mode active
1 = Field length
standard
1 = Swinging
burst detected
1 = Detected.
x
0 = Type 2,
1 = Type 3.
1 = Detected.
x
x
1 = Detected.
x
1 = Detected.
x
1 = Detected.
x
x
x
Unfiltered.
Reserved
x
x
x
x
No function.
Blue screen
output.
x
0x13
Status Register 3
Read only
STATUS_3[7:0]
. Provides
information about the internal status
of the decoder.
x
Reliable
sequence.
Table 183. Register 0x14
Subaddress
0x14
Register
Analog Clamp
Control
Bit Description
Reserved.
Bit
4
0
1
Register Setting
Reserved. Set to default.
I sources switched off.
I sources enabled.
Reserved set to default.
Reserved set to default.
7
0
6
0
5
0
3
0
2
0
1
1
0
0
CCLEN
. Current clamp enable allows the user to
switch off the current sources in the analog front.
Reserved.
Reserved.
Table 184. Register 0x15
Subaddress
0x15
Register
Digital Clamp
Control 1
Bit Description
Reserved
DCT[1:0]
. Digital clamp timing determines the
time constant of the digital fine clamp circuitry.
Bit
4
x
Register Setting
Set to default.
Slow (TC = 1 s).
Medium (TC = 0.5 s).
Fast (TC = 0.1 s).
TC dependant on video.
Set to default.
7
0
6
0
0
1
1
5
0
1
0
1
3
x
2
x
1
x
0
x
Reserved
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