參數(shù)資料
型號(hào)： ADV7189BKSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/104頁(yè)
文件大?。?/td> 0K
描述： IC DECODER VIDEO W/ADC 80LQFP
標(biāo)準(zhǔn)包裝： 1
類型： 視頻解碼器
應(yīng)用： 機(jī)頂盒，視頻播放器，錄音機(jī)
電壓 - 電源，模擬： 3.15 V ~ 3.45 V
電壓 - 電源，數(shù)字： 1.65 V ~ 2 V
安裝類型： 表面貼裝
封裝/外殼： 80-LQFP
供應(yīng)商設(shè)備封裝： 80-LQFP（14x14）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 788 (CN2011-ZH PDF)
ADV7189B
Rev. B | Page 12 of 104
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
Function
3, 9, 14, 31, 71
DGND
G
Digital Ground.
39, 40, 47, 53,
56
AGND
G
Analog Ground.
4, 15
DVDDIO
P
Digital I/O Supply Voltage (3.3 V).
10, 30, 72
DVDD
P
Digital Core Supply Voltage (1.8 V).
50
AVDD
P
Analog Supply Voltage (3.3 V).
38
PVDD
P
PLL Supply Voltage (1.8 V).
42, 44, 46, 58,
60, 62, 41, 43,
45, 57, 59, 61
AIN1toAIN12
I
Analog Video Input Channels.
11
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in
132H
Table 86.
13, 16, 25, 63,
65, 69, 70, 77,
78
NC
No Connect Pins.
35 to32, 24 to
17, 8 to 5,
76 to 73
P0–P19
O
Video Pixel Output Port.
2
HS
O
Horizontal Synchronization Output Signal.
1
VS
O
Vertical Synchronization Output Signal.
80
FIELD
O
Field Synchronization Output Signal.
67
SDA
I/O
I2C Port Serial Data Input/Output Pin.
68
SCLK
I
I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
66
ALSB
I
This pin selects the I2C address for the ADV7189B. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
64
RESET
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7189B circuitry.
27
LLC1
O
This is a line-locked output clock for the pixel data output by the ADV7189B. Nominally 27 MHz,
but varies up or down according to video line length.
26
LLC2
O
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189B.
Nominally 13.5 MHz, but varies up or down according to video line length.
29
XTAL
I
This is the input pin for the 28.6363 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
28
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7189B. In crystal mode, the crystal
must be a fundamental crystal.
36
PWRDN
I
A logic low on this pin places the ADV7189B in a power-down mode. Refer to Power
Management Register in the
133H
I2C Register Maps section for more options on power-down
modes for the ADV7189B.
79
OE
I
When set to a logic low, OE enables the pixel output bus, P19 toP0 of the ADV7189B. A logic
high on the OE pin places Pins P19 to P0, HS, VS, SFL into a high impedance state.
37
ELPF
I
The recommended external loop filter must be connected to this ELPF pin, as shown in
134H
Figure 46.
12
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the
subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video
encoder.
51
REFOUT
O
Internal Voltage Reference Output. Refer to
135H
Figure 46 for a recommended capacitor network for
this pin.
52
CML
O
The CML pin is a common-mode level for the internal ADCs. Refer to
136H
Figure 46 for a
recommended capacitor network for this pin.
48, 49
CAPY1, CAPY2
I
ADC’s Capacitor Network. Refer to
137H
Figure 46 for a recommended capacitor network for this pin.
54, 55
CAPC1, CAPC2
I
ADC’s Capacitor Network. Refer to
138H
Figure 46 for a recommended capacitor network for this pin.
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