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參數(shù)資料
| 型號： | ADV7189BKSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DECODER VIDEO W/ADC 80LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 視頻解碼器 |
| 應(yīng)用： | 機頂盒，視頻播放器，錄音機 |
| 電壓 - 電源，模擬： | 3.15 V ~ 3.45 V |
| 電壓 - 電源，數(shù)字： | 1.65 V ~ 2 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 788 (CN2011-ZH PDF) |
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ADV7189B
Rev. B | Page 23 of 104
SRLS Select Raw Lock Signal, Address 0x51[6]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming video.
It reacts quickly.
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
FSCLE FSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status
of the color subcarrier loop is taken into account when the
overall lock status is determined and presented via Bits[1:0]
in Status Register 1. This bit must be set to 0 when operating
the ADV7189B in YPrPb component mode in order to generate
a reliable HLOCK status bit.
Setting FSCLE to 0 (default) makes the overall lock status
dependent on only the horizontal sync lock.
Setting FSCLE to 1 makes the overall lock status dependent on
the horizontal sync lock and FSC lock.
VS_Coast[1:0], Address 0xF9[3:2]
These bits are used to set VS free-run (coast) frequency.
Table 19. VS_COAST[1:0] Function
VS_COAST[1:0]
Description
00 (default)
Auto coast mode—follows VS
frequency from last video input
01
Forces 50 Hz coast mode
10
Forces 60 Hz coast mode
11
Reserved
CIL[2:0] Count Into Lock, Address 0x51[2:0]
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state and reports this via Status 0[1:0]. It counts
the value in lines of video.
Table 20. CIL Function
CIL[2:0]
Description
000
1
001
2
010
5
011
10
100 (default)
100
101
500
110
1000
111
100000
COL[2:0] Count Out-of-Lock, Address 0x51[5:3]
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into unlocked state, and reports this via Status 0[1:0]. It counts
the value in lines of video.
Table 21. COL Function
COL[2:0]
Description
000
1
001
2
010
5
011
10
100 (default)
100
101
500
110
1000
111
100000
SD COLOR CONTROLS
These registers allow the user to control picture appearance
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture clamp-
ing, although both controls affect the signal’s dc level.
CON[7:0] Contrast Adjust, Address 0x08[7:0]
This register allows the user to adjust the contrast of the picture.
Table 22. CON Function
CON[7:0]
Description
0x80 (default)
Gain on luma channel = 1
0x00
Gain on luma channel = 0
0xFF
Gain on luma channel = 2
SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address
0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only. The user can adjust the saturation of the picture.
Table 23. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
Description
0x80 (default)
Chroma gain = 0 dB
0x00
Gain on Cb channel = 42 dB
0xFF
Gain on Cb channel = +6 dB
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7189BKSTZ10F | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BKSTZ10F2 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat SDTV Video Decoder |
| ADV7189BST | 制造商:Analog Devices 功能描述: |
| ADV7189KST | 制造商:Rochester Electronics LLC 功能描述:12BIT NTSC/PAL/SECAMVIDDECOD I.C. - Tape and Reel 制造商:Analog Devices 功能描述:IC VIDEO ENCODER |
| ADV7189XST | 制造商:Analog Devices 功能描述:54MHZ NTSC/PAL ENCODER(DNR+MACROVISON)IC - Bulk |
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