參數(shù)資料
型號(hào)： ADV7180BCPZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： 10-Bit, 4 x Oversampling SDTV Video Decoder
中文描述： COLOR SIGNAL DECODER, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件頁(yè)數(shù)： 46/112頁(yè)
文件大?。?/td> 1320K
代理商： ADV7180BCPZ
ADV7180
NVBEGDELO, NTSC VSYNC Begin Delay on Odd Field,
Address 0xE5 [7]
When NVBEGDELO is 0 (default), there is no delay.
Setting NVBEGDELO to 1 delays VSYNC going high on an odd
field by a line relative to NVBEG.
Rev. A | Page 46 of 112
For all NTSC/PAL VSYNC timing controls, both the V bit in
the AV code and the VSYNC on the VS pin are modified.
ADVANCE END OF
VSYNC BY NVEND[4:0]
DELAY END OF VSYNC
BY NVEND[4:0]
VSYNC END
NVENDSIGN
ODD FIELD
0
1
NO
YES
NVENDDELO
VSEHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NVENDDELE
VSEHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
0
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
VSYNC BEGIN
NVBEGSIGN
ODD FIELD
0
1
NO
YES
NVBEGDELO
VSBHO
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NVBEGDELE
VSBHE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
1
0
1
0
NOT VALID FOR USER
PROGRAMMING
0
Figure 36. NTSC Vsync End
NVENDDELO, NTSC Vsync End Delay on Odd Field,
Address 0xE6 [7]
When NVENDDELO is 0 (default), there is no delay.
Setting NVENDDELO to 1 delays vsync from going low on an
odd field by a line relative to NVEND.
NVENDDELE, NTSC Vsync End Delay on Even Field,
Address 0xE6 [6]
When NVENDDELE is set to 0 (default), there is no delay.
Setting NVENDDELE to 1 delays vsync from going low on an
even field by a line relative to NVEND.
NVENDSIGN, NTSC Vsync End Sign, Address 0xE6 [5]
Setting NVENDSIGN to 0 (default) delays the end of vsync.
Set for user manual programming.
Setting NVENDSIGN to 1 advances the end of vsync. Not
recommended for user programming.
Figure 35. NTSC Vsync Begin
NVBEGDELE, NTSC Vsync Begin Delay on Even Field,
Address 0xE5 [6]
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays vsync going high on an even
field by a line relative to NVBEG.
NVBEGSIGN, NTSC Vsync Begin Sign, Address 0xE5 [5]
Setting NVBEGSIGN to 0 delays the start of vsync. Set for user
manual programming.
Setting NVBEGSIGN to 1 (default) advances the start of vsync.
Not recommended for user programming.
NVBEG[4:0], NTSC Vsync Begin, Address 0xE5 [4:0]
The default value of NVBEG is 00101, indicating the NTSC
vsync begin position.
相關(guān)PDF資料
PDF描述
ADV7180BSTZ 10-Bit, 4 x Oversampling SDTV Video Decoder
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7180BCPZ 制造商:Analog Devices 功能描述:IC VIDEO DECODER 10BIT 57.27MSPS LFCSP40
ADV7180BCPZ-REEL 功能描述:IC VIDEO DECODER SDTV 40-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
ADV7180BST48Z 功能描述:IC VID DECOD SDTV 10BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤(pán) 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND
ADV7180BST48Z-RL 功能描述:視頻 IC 48-Lead Low Profile Quad Flat Package RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
ADV7180BSTZ 功能描述:IC VIDEO DECODER SDTV 64-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機(jī)/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤(pán) 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND
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