參數(shù)資料
型號(hào)： ADV7179KCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 24/52頁(yè)
文件大?。?/td> 0K
描述： IC ENCODER VID NTSC/PAL 40LFCSP
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻編碼器
應(yīng)用： 數(shù)碼相機(jī)，手機(jī)，便攜式視頻
電壓 - 電源，模擬： 2.8 V，3.3 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 40-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 40-LFCSP-VQ（6x6）
包裝： 托盤(pán)
產(chǎn)品目錄頁(yè)面： 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 30 of 52
MODE REGISTER 2 (MR2)
Bits:
MR27–MR20
Address:
SR4–SR0 = 02H
Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can
be read from as well as written to.
MR21
MR27
MR22
MR23
MR26
MR25
MR24
MR20
CHROMINANCE
CONTROL
0
ENABLE COLOR
1
DISABLE COLOR
MR24
GENLOCK CONTROL
x
DISABLE GENLOCK
0
ENABLE SUBCARRIER
RESET PIN
1
0
1
ENABLE RTC PIN
MR22 MR21
LOW POWER MODE
0
DISABLE
1
ENABLE
MR26
SQUARE PIXEL
CONTROL
0
DISABLE
1
ENABLE
MR20
BURST
CONTROL
0
ENABLE BURST
1
DISABLE BURST
MR25
MR27
ACTIVE VIDEO LINE
DURATION
0
720 PIXELS
1
710 PIXELS/702 PIXELS
MR23
RESERVED
02980-A
-039
Figure 40. Mode Register 2
Table 11. MR2 Bit Description
Bit Name
Bit No.
Description
Square Pixel Control
MR20
This bit is used to set up square pixel mode. This is available in slave mode only. For NTSC, a
24.5454 MHz clock must be supplied. For PAL, a 29.5 MHz clock must be supplied.
Genlock Control
MR22–MR21
These bits control the genlock feature of the ADV7174/ ADV7179. Setting MR21 to Logic 1
configures the SCRESET/RTC pin as an input. Setting MR22 to Logic 0 configures the
SCRESET/RTC pin as a subcarrier reset input. Therefore, the subcarrier will reset to Field 0
following a low-to-high transition on the SCRESET/RTC pin. Setting MR22 to Logic 1 configures
the SCRESET/RTC pin as a real-time control input.
Active Video Line Duration
MR23
This bit switches between two active video line durations. A 0 selects CCIR REC601 (720 pixels
PAL/NTSC), and a 1 selects ITU-R.BT470 standard for active video duration (710 pixels NTSC
and 702 pixels PAL).
Chrominance Control
MR24
This bit enables the color information to be switched on and off the video output.
Burst Control
MR25
This bit enables the burst information to be switched on and off the video output.
Low Power Mode
MR26
This bit enables the lower power mode of the ADV7174/ADV7179. This reduces the DAC
current by 45%.
Reserved
MR27
A Logic 0 must be written to this bit.
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