參數(shù)資料
型號(hào): ADV7179KCPZ
廠商: Analog Devices Inc
文件頁數(shù): 14/52頁
文件大?。?/td> 0K
描述: IC ENCODER VID NTSC/PAL 40LFCSP
產(chǎn)品培訓(xùn)模塊: Interfacing AV Converters to Blackfin Processors
標(biāo)準(zhǔn)包裝: 1
類型: 視頻編碼器
應(yīng)用: 數(shù)碼相機(jī),手機(jī),便攜式視頻
電壓 - 電源,模擬: 2.8 V,3.3 V
安裝類型: 表面貼裝
封裝/外殼: 40-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 40-LFCSP-VQ(6x6)
包裝: 托盤
產(chǎn)品目錄頁面: 786 (CN2011-ZH PDF)
ADV7174/ADV7179
Rev. B | Page 21 of 52
Mode 1: Master Option HSYNC, BLANK, FIELD
(Timing Register 0 TR0 = X X X X X 0 1 1)
In this mode, the ADV7174/ADV7179 can generate horizontal
SYNC and odd/even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, the ADV7174/ADV7179 automatically blanks all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
Mode 1 is illustrated in
(NTSC) and
(PAL).
illustrates the
HSYNC, BLANK, and FIELD for an
odd or even field transition relative to the pixel data.
FIELD
PIXEL
DATA
PAL = 12
× CLOCK/2
NTSC = 16
× CLOCK/2
PAL = 132
× CLOCK/2
NTSC = 122
× CLOCK/2
Cb
Y
Cr
Y
HSYNC
BLANK
02980-A
-026
Figure 26. Timing Mode 1 Odd/Even Field Transitions Master/Slave
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