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參數(shù)資料
| 型號： | ADV3002BSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SWITCH HDMI/DVI 4:1 80LQFP |
| 產(chǎn)品變化通告： | Marking Change 25/Mar/2009 |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 功能： | 開關(guān) |
| 電路： | 1 x 4:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應(yīng)商設(shè)備封裝： | 80-LQFP（14x14） |
| 包裝： | 托盤 |
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Data Sheet
ADV3002
Rev. B | Page 13 of 28
For example, interlayer vias can be used to route the ADV3002
TMDS outputs on multiple layers of the printed circuit board
(PCB) without severely degrading the quality of the output signal.
The output has a disable feature that places the outputs in tristate
mode. Bigger wire-OR’ed arrays can be constructed using the
ADV3002 in this mode.
The ADV3002 requires output termination resistors when the high
speed outputs are enabled. Termination can be internal and/or
external. The internal terminations of the ADV3002 are enabled
by default after reset. External terminations can be provided either
by on-board resistors or by the input termination resistors of an
HDMI/DVI receiver. If both the internal terminations are enabled
and external terminations are present, set the output current level
to 20 mA by programming the TX_OCL bit of the TMDS output
control register, as shown in Table 10 (20 mA is the default
upon reset). If only external terminations are provided (if the
internal terminations are disabled), set the output current level
to 10 mA by programming the TX_OCL bit of the TMDS output
control register. The high speed outputs must be disabled if
there are no output termination resistors present in the system.
DDC BUFFERS
The DDC buffers are 5 V tolerant bidirectional lines that carry
extended display identification data (EDID) and high bandwidth
digital content protection (HDCP) encryption. The ADV3002
provides switching and buffering for the DDC buses. The DDC
buffers are bidirectional, and fully support arbitration, clock
synchronization, and other relevant features of a standard
mode I2C bus.
EDID REPLICATION
The ADV3002 EDID replication feature reduces the total system
cost by eliminating the need for an EDID EEPROM for each
HDMI port. With the ADV3002, only a single external EDID is
necessary. The ADV3002 stores the EDID information in an
on-chip SRAM. This enables the EDID information to be simulta-
neously accessible to all four HDMI ports. The ADV3002
combines the 5 V power from the four HDMI sources such that
the EDID information can be available even when the system
power is off. A block diagram of the ADV3002 DDC buffering
and EDID replication scheme is shown in Figure 27.
HDMI
PORT A
HDMI
PORT B
HDMI
PORT C
HDMI
PORT D
2
SRAM
EDID
CONTROL
I2C
MASTER
EXTERNAL
EDID
EEPROM
v1.3
MCU
I2C
READ/
WRITE
SLAVE
I2C
READ/
WRITE
SLAVE
I2C
READ
SLAVE
I2C
READ
SLAVE
DDC
MUX
HDMI
Rx
I2C
READ
SLAVE
EDID_[SCL/SDA]
I2C_[SCL/SDA]
07905-
007
Figure 27. EDID Replication Block Diagram
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參數(shù)描述 |
|---|---|
| ADV3002BSTZ-RL | 功能描述:IC SWITCH HDMI/DVI 4:1 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 模擬開關(guān)，多路復(fù)用器，多路分解器 系列:- 其它有關(guān)文件:STG4159 View All Specifications 標(biāo)準(zhǔn)包裝:5,000 系列:- 功能:開關(guān) 電路:1 x SPDT 導(dǎo)通狀態(tài)電阻:300 毫歐 電壓電源:雙電源 電壓 - 電源，單路/雙路(±):±1.65 V ~ 4.8 V 電流 - 電源:50nA 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:7-WFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:7-覆晶 包裝:帶卷 (TR) |
| ADV3002-EVALZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:4:1 HDMI/DVI Switch with Equalization, DDC/CEC Buffers and EDID Replication |
| ADV3002XSTZ | 功能描述:IC SWITCH HDMI/DVI 4:1 80LQFP 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態(tài):上次購買時間 類型:視頻開關(guān) 應(yīng)用:HDTV，投影儀，機頂盒 安裝類型:- 封裝/外殼:- 供應(yīng)商器件封裝:- 標(biāo)準(zhǔn)包裝:1 |
| ADV3002XSTZ-RL | 功能描述:IC SWITCH HDMI/DVI 4:1 80LQFP 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 類型:視頻開關(guān) 應(yīng)用:HDTV，投影儀，機頂盒 安裝類型:- 封裝/外殼:- 供應(yīng)商器件封裝:- 標(biāo)準(zhǔn)包裝:1 |
| ADV3003 | 制造商:AD 制造商全稱:Analog Devices 功能描述:HDMI/DVI TMDS Equalizer |
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