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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 80/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
Rev. A | Page 80 of 92
0
LATCH
ADuC7026/
ADuC7027
AD15:0
A16
EPROM
64k × 16-BIT
A0:15
D0–D15
CS
RAM
128k × 8-BIT
D0–D7
A0:15
A16
CS
WE
OE
WE
OE
AE
MS0
MS1
WS
RS
Figure 68. Interfacing to External EPROM/RAM
XMCFG Register
Name
XMCFG
Address
0xFFFFF000
Default Value
0x00
Access
R/W
XMCFG is set to 1 to enable external memory access. This must
be set to 1 before any port pins function as external memory
access pins. The port pins must also be individually enabled via
the GPxCON MMR.
XMxCON Registers
Name
XM0CON
XM1CON
XM2CON
XM3CON
Address
0xFFFFF010
0xFFFFF014
0xFFFFF018
0xFFFFF01C
Default Value
0x00
0x00
0x00
0x00
Access
R/W
R/W
R/W
R/W
XMxCON are the control registers for each memory region.
They allow the enabling/disabling of a memory region and
control the data bus width of the memory region.
Table 80. XMxCON MMR Bit Descriptions
Bit
Description
1
Selects Between 8-Bit and 16-Bit Data Bus Width.
Set
by the
user to select a 16-bit data bus.
Cleared
by the user to
select an 8-bit data bus.
0
Enables Memory Region
. Set
by the user to enable memory
region.
Cleared
by the user to disable the memory region.
XMxPAR Registers
Name
XM0PAR
XM1PAR
XM2PAR
XM3PAR
Address
0xFFFFF020
0xFFFFF024
0xFFFFF028
0xFFFFF02C
Default Value
0x70FF
0x70FF
0x70FF
0x70FF
Access
R/W
R/W
R/W
R/W
XMxPAR are registers that define the protocol used for
accessing the external memory for each memory region.
Table 81. XMxPAR MMR Bit Descriptions
Bit
Description
15
Enable Byte Write Strobe. This bit is only used for two, 8-
bit memory sharing the same memory region.
Set
by
the user to gate the A0 output with the WR output. This
allows byte write capability without using BHE and BLE
signals.
Cleared
by user to use BHE and BLE signals.
14:12
Number of wait states on the address latch enable
strobe.
11
Reserved.
10
Extra Address Hold Time.
Set
by the user to disable extra
hold time.
Cleared
by the user to enable one clock cycle
of hold on the address in read and write.
9
Extra bus transition time on read.
Set
by the user to disable
extra bus transition time.
Cleared
by the user to enable
one extra clock before and after the read strobe (RS).
8
Extra Bus Transition Time On Write.
Set
by the user to
disable extra bus transition time.
Cleared
by the user to
enable one extra clock before and after the write strobe
(WS).
7:4
Number of Write Wait States. Select the number of wait
states added to the length of the WS pulse. 0x0 is 1clock;
0xF is 16 clock cycles (default value).
3:0
Number of Read Wait States. Select the number of wait
states added to the length of the RS pulse. 0x0 is 1 clock;
0xF is 16 clock cycles (default value).
Figure 69, Figure 70, Figure 71, and Figure 72 show the timing
for a read cycle, a read cycle with address hold and bus turn
cycles, a write cycle with address and write hold cycles, and a
write cycle with wait sates, respectively.
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