參數(shù)資料
型號: ADUuC7027BSTZ62-RL
廠商: Analog Devices, Inc.
英文描述: Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU
中文描述: 精密模擬微控制器的12位模擬I / O,ARM7TDMI的微控制器
文件頁數(shù): 66/92頁
文件大?。?/td> 850K
代理商: ADUUC7027BSTZ62-RL
ADuC7019/20/21/22/24/25/26/27
SCL (Serial Clock) I/O Pin
Rev. A | Page 66 of 92
The master serial clock (SCL) is used to synchronize the data
being transmitted and received through the MOSI SCL period.
Therefore, a byte is transmitted/received after eight SCL
periods. The SCL pin is configured as an output in master mode
and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
f
f
clock
serial
+
×
)
1
2
SPIDIV
UCLK
=
The maximum speed of the SPI clock is dependant on the clock
divider bits and is summarized in Table 57.
Table 57. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
0
1
2
SPIDIV in
hex
SPI speed
in MHz
3
0x2F
4
0x5F
5
0xBF
0x05
0x0B
0x17
3.482
1.741
0.870
0.435
0.218
0.109
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 10.4 Mb at CD = 0.
The formula to determine the maximum speed is as follow:
4
HCLK
k
serialcloc
f
f
=
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is
important that the polarity and phase are configured the same
for the master and slave devices.
Chip Select (CS) Input Pin
In SPI slave mode, a transfer is initiated by the assertion of CS ,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of CS. In slave mode, CS is always an input.
SPI Registers
The following MMR registers are used to control the SPI
interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.
SPISTA Register
Name
SPISTA
Address
0xFFFF0A00
Default Value
0x00
Access
R/W
SPISTA is an 8-bit read-only status register. Only Bit 1 or Bit 4
of this register generates an interrupt. Bit 6 of the SPICON
register determines which bit generates the interrupt.
Table 58. SPISTA MMR Bit Descriptions
Bit
Description
7:6
Reserved.
5
SPIRX Data Register Overflow Status Bit.
Set
if SPIRX is
overflowing.
Cleared
by reading SPIRX register.
4
SPIRX Data Register IRQ.
Set
automatically if Bit 3 or Bit 5
is set.
Cleared
by reading SPIRX register.
3
SPIRX Data Register Full Status Bit.
Set
automatically if a
valid data is present in the SPIRX register.
Cleared
by
reading SPIRX register.
2
SPITX Data Register Underflow Status Bit.
Set
auto-
matically if SPITX is under flowing.
Cleared
by writing in
the SPITX register.
1
SPITX Data Register IRQ.
Set
automatically if Bit 0 is clear
or Bit 2 is set.
Cleared
by writing in the SPITX register or if
finished transmission disabling the SPI.
0
SPITX Data Register Empty Status Bit.
Set
by writing to
SPITX to send data. This bit is set during transmission of
data.
Cleared
when SPITX is empty.
SPIRX Register
Name
Address
SPIRX
0xFFFF0A04
Default Value
0x00
Access
R
SPIRX is an 8-bit read-only receive register.
SPITX Register
Name
SPITX
Address
0xFFFF0A08
Default Value
0x00
Access
W
SPITX is an 8-bit write-only transmit register.
SPIDIV Register
Name
SPIDIV
Address
0xFFFF0A0C
Default Value
0x1B
Access
R/W
SPIDIV is an 8-bit serial clock divider register.
SPICON Register
Name
SPICON
Address
0xFFFF0A10
Default Value
0x0000
Access
R/W
SPICON is a 16-bit control register.
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