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| 型號： | ADUuC7027BSTZ62-RL |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI MCU |
| 中文描述： | 精密模擬微控制器的12位模擬I / O，ARM7TDMI的微控制器 |
| 文件頁數(shù)： | 75/92頁 |
| 文件大?。?/td> | 850K |
| 代理商： | ADUUC7027BSTZ62-RL |
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ADuC7019/20/21/22/24/25/26/27
FIQSTA Register
Name
FIQSTA
FIQSIG Register
Name
FIQSIG
FIQEN Register
Name
FIQEN
FIQCLR Register
Name
FIQCLR
Rev. A | Page 75 of 92
Address
0xFFFF0100
Default Value
0x00000000
Access
R
Address
0xFFFF0104
Default Value
0x00XXX000
Access
R
Address
0xFFFF0108
Default Value
0x00000000
Access
R/W
Address
0xFFFF010C
Default Value
0x00000000
Access
W
Bit 31 to Bit 1 of FIQSTA are logically OR’ed to create the FIQ
signal to the core and Bit 0 of both the FIQ and IRQ registers
(FIQ source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. A bit set to 1
in FIQEN does, as a side effect, clear the same bit in IRQEN.
Also, a bit set to 1 in IRQEN does, as a side effect, clear the
same bit in FIQEN. An interrupt source can be disabled in both
IRQEN and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are nonmaskable, they are
controlled by another register, SWICFG, which simultaneously
writes into the IRQSTA and IRQSIG registers, and/or the
FIQSTA and FIQSIG registers. The 32-bit register dedicated to
software interrupt is SWICFG described in Table 73. This MMR
allows the control of programmed source interrupt.
SWICFG Register
Name
SWICFG
Table 73. SWICFG MMR Bit Descriptions
Bit
Description
31:3
Reserved.
2
Programmed Interrupt-FIQ.
Setting/Clearing
this bit
corresponds with setting/clearing Bit 1 of FIQSTA
and FIQSIG.
1
Programmed Interrupt-IRQ.
Setting/Clearing
this bit
corresponds with setting/clearing Bit 1 of IRQSTA
and IRQSIG.
0
Reserved.
Address
0xFFFF0010
Default Value
0x00000000
Access
W
Note that any interrupt signal must be active for at least the
equivalent of the interrupt latency time, to be detected by the
interrupt controller and to be detected by the user in the
IRQSTA/FIQSTA register.
TIMERS
The ADuC7019/7020/7021/7022/7024/7025/7026/7027 have
four general-purpose timer/counters:
Timer0
Timer1
Timer2 or Wake-Up Timer
Timer3 or Watchdog Timer
These four timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, the counter decreases from the
maximum value until zero scale and starts again at the
minimum value. (It also increases from the minimum value
until full scale and starts again at the maximum value.)
In periodic mode, the counter decrements/increments from the
value in the load register (T×LD MMR) until zero/full scale and
starts again at the value stored in the load register.
The timer interval is calculated as follow:
(
)
clock
source
prescaler
LD
T
Interval
×
×
=
The value of a counter can be read at any time by accessing
its value register (T×VAL). Note that when a timer is being
clocked from a clock other than core clock, an incorrect value
could be read (due to asynchronous clock system). In this
configuration, T×VAL should always be read twice. If the two
readings are different, then it should be read a third time to
get the correct value.
Timers are started by writing in the control register of the
corresponding timer (T×CON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (T×CLRI).
When using an asynchronous clock-to-clock timer, the interrupt
in the timer block could take more time to clear than the time it
takes for the code in the interrupt routine to execute. Ensure that
the interrupt signal is cleared before leaving the interrupt service
routine. This can be done by checking the IRQSTA MMR.
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