參數(shù)資料
型號(hào): ADUC848BSZ32-5
廠商: Analog Devices Inc
文件頁(yè)數(shù): 73/108頁(yè)
文件大小: 0K
描述: IC MCU FLASH W/16BIT ADC 52MQFP
標(biāo)準(zhǔn)包裝: 1
系列: MicroConverter® ADuC8xx
核心處理器: 8052
芯體尺寸: 8-位
速度: 12.58MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: POR,PSM,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 34
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 4.75 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x16b; D/A 1x12b,2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 52-QFP
包裝: 托盤
Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 67 of 108
DUAL DATA POINTERS
The parts incorporate two data pointers. The second data
pointer is a shadow data pointer and is selected via the data
pointer control SFR (DPCON). DPCON features automatic
hardware post-increment and post-decrement as well as an
automatic data pointer toggle.
DPCON—Data Pointer Control SFR
SFR Address:
A7H
Power-On Default:
00H
Bit Addressable:
No
Table 42. DPCON SFR Bit Designations
Bit No.
Name
Description
7
----
Not Implemented. Write Don’t Care.
6
DPT
Data Pointer Automatic Toggle Enable.
Cleared by the user to disable autoswapping of the DPTR.
Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction.
5, 4
DP1m1, DP1m0
Shadow Data Pointer Mode. These bits enable extra modes of the shadow data pointer operation, allowing
more compact and more efficient code size and execution.
DP1m1
DP1m0
Behavior of the Shadow Data Pointer
0
8052 behavior.
0
1
DPTR is post-incremented after a MOVX or a MOVC instruction.
1
0
DPTR is post-decremented after a MOVX or MOVC instruction.
1
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction can be useful for
moving 8-bit blocks to/from 16-bit devices.)
3, 2
DP0m1, DP0m0
Main Data Pointer Mode. These bits enable extra modes of the main data pointer operation, allowing more
compact and more efficient code size and execution.
DP0m1
DP0m0
Behavior of the Main Data Pointer
0
8052 behavior.
0
1
DPTR is post-incremented after a MOVX or a MOVC instruction.
1
0
DPTR is post-decremented after a MOVX or MOVC instruction.
1
DPTR LSB is toggled after a MOVX or MOVC instruction. (This instruction is useful for
moving 8-bit blocks to/from 16-bit devices.)
1
----
Not Implemented. Write Don’t Care.
0
DPSEL
Data Pointer Select.
Cleared by the user to select the main data pointer. This means that the contents of this 24-bit register are
placed into the DPL, DPH, and DPP SFRs.
Set by the user to select the shadow data pointer. This means that the contents of a separate 24-bit register
appear in the DPL, DPH, and DPP SFRs.
Note the following:
The Dual Data Pointer section is the only place in which
main and shadow data pointers are distinguished.
Whenever the DPTR is mentioned elsewhere in this data
sheet, active DPTR is implied.
Only the MOVC/MOVX @DPTR instructions
automatically post-increment and post-decrement the
DPTR. Other MOVC/MOVX instructions, such as MOVC
PC or MOVC @Ri, do not cause the DPTR to automatically
post-increment and post-decrement.
To illustrate the operation of DPCON, the following code copies
256 bytes of code memory at Address D000H into XRAM,
starting from Address 0000H.
MOV DPTR,#0
;Main DPTR = 0
MOV DPCON,#55H
;Select shadow DPTR
;DPTR1 increment mode
;DPTR0 increment mode
;DPTR auto toggling ON
MOV DPTR,#0D000H ;DPTR = D000H
MOVELOOP: CLR A
MOVC A,@A+DPTR
;Get data
;Post Inc DPTR
;Swap to Main DPTR(Data)
MOVX @DPTR,A
;Put ACC in XRAM
;Increment main DPTR
;Swap Shadow DPTR(Code)
MOV A, DPL
JNZ MOVELOOP
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