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| 型號(hào)： | ADUC848BSZ32-5 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 53/108頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH W/16BIT ADC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，PWM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 32KB（32K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大小： | 4K x 8 |
| RAM 容量： | 2.25K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.75 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x16b; D/A 1x12b，2x16b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤 |
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Data Sheet
ADuC845/ADuC847/ADuC848
Rev. C | Page 49 of 108
40
60
70
90
TJ JUNCTION TEMPERATURE (C)
RE
TE
NTION
(Years)
250
200
150
100
50
0
50
80
110
300
100
ADI SPECIFICATION
100 YEARS MIN.
AT TJ = 55C
04741-028
Figure 27. Flash/EE Memory Data Retention
FLASH/EE PROGRAM MEMORY
The ADuC845/ADuC847/ADuC848 contain a 64-kbyte array of
Flash/EE program memory. The lower 62 kbytes of this program
memory are available to the user for program storage or as
additional NV data memory.
The upper 2 kbytes of this Flash/EE program memory array
contain permanently embedded firmware, allowing in-circuit
serial download, serial debug, and nonintrusive single-pin
emulation. These 2 kbytes of embedded firmware also contain
a power-on configuration routine that downloads factory cali-
brated coefficients to the various calibrated peripherals such
as ADC, temperature sensor, current sources, band gap, and
references.
These 2 kbytes of embedded firmware are hidden from the user
code. Attempts to read this space read 0s; therefore, the embed-
ded firmware appears as NOP instructions to user code.
In normal operating mode (power-on default), the 62 kbytes of
user Flash/EE program memory appear as a single block. This
block is used to store the user code as shown in Figure 28.
EMBEDDED DOWNLOAD/DEBUG KERNEL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS
CODE TO BE DOWNLOADED TO ANY OF THE
62 kBYTES OF ON-CHIP PROGRAM MEMORY.
THE KERNEL PROGRAM APPEARS AS NOP
INSTRUCTIONS TO USER CODE.
62 kBYTES OF FLASH/EE PROGRAM MEMORY
ARE AVAILABLE TO THE USER. ALL OF THIS
SPACE CAN BE PROGRAMMED FROM THE
PERMANENTLY EMBEDDED DOWNLOAD/DEBUG
KERNEL OR IN PARALLEL PROGRAMMING MODE.
USER PROGRAM MEMORY
FFFFH
2kBYTE
F800H
F7FFH
62kBYTE
0000H
04741-029
Figure 28. Flash/EE Program Memory Map in Normal Mode
In normal mode, the 62 kbytes of Flash/EE program memory
can be programmed by serial downloading and by parallel
programming.
Serial Downloading (In-Circuit Programming)
The ADuC845/ADuC847/ADuC848 facilitate code download
via the standard UART serial port. The parts enter serial down-
load mode after a reset or a power cycle if the PSEN pin is pulled
low through an external 1 kΩ resistor. Once in serial download
mode, the hidden embedded download kernel executes. This
allows the user to download code to the full 62 kbytes of Flash/EE
program memory while the device is in circuit in its target
application hardware.
A PC serial download executable (WSD.EXE) is provided as
part of the ADuC845/ADuC847/ADuC848 Quick Start
development system. Application Note uC004 fully describes
the serial download protocol that is used by the embedded
download kernel. This application note is available at
www.analog.com/microconverter.
Parallel Programming
The parallel programming mode is fully compatible with
conventional third-party flash or EEPROM device programmers.
A block diagram of the external pin configuration required to
support parallel programming is shown in Figure 29. In this
mode, Ports 0 and 2 operate as the external address bus interface,
P3 operates as the external data bus interface, and P1.0 operates
as the write enable strobe. P1.1, P1.2, P1.3, and P1.4 are used as
general configuration ports that configure the device for various
program and erase operations during parallel programming.
P1.4–P1.1
P3.7–P3.0
EA
RESET
ADuC845/
ADuC847/
ADuC848
+5V
COMMAND
P1.7–P1.5
TIMING
DATA
04741-030
ENABLE
GND
VDD
P1.0
Figure 29. Flash/EE Memory Parallel Programming
The command words that are assigned to P1.1, P1.2, P1.3, and
P1.4 are described in Table 31.
Table 31. Flash/EE Memory Parallel Programming Modes
Port 1 Pins
P1.4
P1.3
P1.2
P1.1
Programming Mode
0
Erase Flash/EE Program, Data, and
Security Mode
1
0
1
0
Program Code Byte
0
1
0
Program Data Byte
1
0
1
Read Code Byte
0
1
Read Data Byte
1
0
Program Security Modes
1
0
1
Read/Verify Security Modes
All other codes
Redundant
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