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參數(shù)資料
| 型號(hào)： | ADUC824BSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 59/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8K FLASH ADC/DAC 52MQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC8xx |
| 核心處理器： | 8052 |
| 芯體尺寸： | 8-位 |
| 速度： | 12.58MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | POR，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲(chǔ)器容量： | 8KB（8K x 8） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 640 x 8 |
| RAM 容量： | 256 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 5.25 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 3x16b，4x24b; D/A 1x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 52-QFP |
| 包裝： | 托盤(pán) |
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REV. B
ADuC824
–62–
ADuC824 HARDWARE DESIGN CONSIDERATIONS
This section outlines some of the key hardware design consider-
ations that must be addressed when integrating the ADuC824
into any hardware system.
Clock Oscillator
As described earlier, the core clock frequency for the ADuC824
is generated from an on-chip PLL that locks onto a multiple
(384 times) of 32.768 kHz. The latter is generated from an inter-
nal clock oscillator. To use the internal clock oscillator, connect
a 32.768 kHz parallel resonant crystal between XTAL1 and
XTAL2 pins (32 and 33) as shown in Figure 43.
As shown in the typical external crystal connection diagram in
Figure 44, two internal 12 pF capacitors are provided on-chip.
These are connected internally, directly to the XTAL1 and
XTAL2 pins and the total input capacitances at both pins is
detailed in the specification section of this data sheet. The value
of the total load capacitance required for the external crystal
should be the value recommended by the crystal manufacturer
for use with that specific crystal. In many cases, because of the
on-chip capacitors, additional external load capacitors will not
be required.
XTAL2
XTAL1
32.768kHz
TO INTERNAL
PLL
ADuC824
12pF
Figure 43. External Parallel Resonant Crystal Connections
External Memory Interface
In addition to its internal program and data memories, the
ADuC824 can access up to 64 Kbytes of external program memory
(ROM/PROM/etc.) and up to 16 Mbytes of external data
memory (SRAM).
To select from which code space (internal or external program
memory) to begin executing instructions, tie the
EA (external
access) pin high or low, respectively. When
EA is high (pulled up
to VDD), user program execution will start at address 0 of the
internal 8 Kbytes Flash/EE code space. When
EA is low (tied to
ground) user program execution will start at address 0 of the
external code space. In either case, addresses above 1FFF hex
(8K) are mapped to the external space.
Note that a second very important function of the
EA pin is
described in the Single Pin Emulation Mode section of this
data sheet.
External program memory (if used) must be connected to the
ADuC824 as illustrated in Figure 44. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during external
program memory fetches. Port 0 (P0) serves as a multiplexed
address/data bus. It emits the low byte of the program counter
(PCL) as an address, and then goes into a float state awaiting
the arrival of the code byte from the program memory. During the
time that the low byte of the program counter is valid on P0, the
signal ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2) emits the high byte of
the program counter (PCH), then
PSEN strobes the EPROM
and the code byte is read into the ADuC824.
LATCH
EPROM
OE
A8–A15
A0–A7
D0–D7
(INSTRUCTION)
ADuC824
PSEN
P2
ALE
P0
Figure 44. External Program Memory Interface
Note that program memory addresses are always 16 bits wide, even
in cases where the actual amount of program memory used is less
than 64 Kbytes. External program execution sacrifices two of the
8-bit ports (P0 and P2) to the function of addressing the program
memory. While executing from external program memory, Ports
0 and 2 can be used simultaneously for read/write access to exter-
nal data memory, but not for general-purpose I/O.
Though both external program memory and external data memory
are accessed by some of the same pins, the two are completely
independent of each other from a software point of view. For
example, the chip can read/write external data memory while
executing from external program memory.
Figure 45 shows a hardware configuration for accessing up to
64 Kbytes of external RAM. This interface is standard to any 8051
compatible MCU.
LATCH
SRAM
OE
A8–A15
A0–A7
D0–D7
(DATA)
ADuC824
RD
P2
ALE
P0
WE
WR
Figure 45. External Data Memory Interface (64 K Address
Space)
If access to more than 64 Kbytes of RAM is desired, a feature
unique to the ADuC824 allows addressing up to 16 Mbytes
of external RAM simply by adding an additional latch as illustrated
in Figure 46.
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