參數(shù)資料
型號(hào)： ADUC824BSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 33/68頁(yè)
文件大?。?/td> 0K
描述： IC MCU 8K FLASH ADC/DAC 52MQFP
標(biāo)準(zhǔn)包裝： 1
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 12.58MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 34
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.25 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 3x16b，4x24b; D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 52-QFP
包裝： 托盤
REV. B
ADuC824
–39–
Table XII. Flash/EE Memory Parallel Programming Modes
Port 3 Pins
Programming
0.7
0.6
0.5
0.4
0.3
0.2
0.1
Mode
XXXX
000Erase Flash/EE
Program, Data, and
Security Modes
XXXX
001Read Device
Signature/ID
X
1010Program Code Byte
X
0010Program Data Byte
X
1011Read Code Byte
X
0011Read Data Byte
XXXX
100Program Security
Modes
XXXX
101Read/Verify Security
Modes
All other codes
Redundant
Flash/EE Program Memory Security
The ADuC824 facilitates three modes of Flash/EE program
memory security. These modes can be independently activated,
restricting access to the internal code space. These security
modes can be enabled as part of the user interface available on all
ADuC824 serial or parallel programming tools referenced on the
MicroConverter web page at www.analog.com/microconverter.
The security modes available on the ADuC824 are described
as follows:
Lock Mode
This mode locks code in memory, disabling parallel programming
of the program memory although reading the memory in parallel
mode is still allowed. This mode is deactivated by initiating a
“code-erase” command in serial download or parallel program-
ming modes.
Secure Mode
This mode locks code in memory, disabling parallel programming
(program and verify/read commands) as well as disabling the
execution of a ‘MOVC’ instruction from external memory,
which is attempting to read the op codes from internal memory.
This mode is deactivated by initiating a “code-erase” command
in serial download or parallel programming modes.
Serial Safe Mode
This mode disables serial download capability on the device. If
Serial Safe mode is activated and an attempt is made to reset
the part into serial download mode, i.e., RESET asserted and
deasserted with
PSEN low, the part will interpret the serial
download reset as a normal reset only. Therefore, it will not
enter serial download mode but only execute a normal reset
sequence. Serial Safe mode can only be disabled by initiating a
code-erase command in parallel programming mode.
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH) 4-byte pages as shown in
Figure 30.
9FH
BYTE 1
BYTE 2
BYTE 3
BYTE 4
00H
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Figure 30. Flash/EE Data Memory Configuration
As with other ADuC824 user-peripheral circuits, the interface to
this memory space is via a group of registers mapped in the SFR
space. A group of four data registers (EDATA1–4) are used to
hold 4-byte page data just accessed. EADRL is used to hold the
8-bit address of the page to be accessed. Finally, ECON is an
8-bit control register that may be written with one of five Flash/EE
memory access commands to trigger various read, write, erase, and
verify functions. These registers can be summarized as follows:
ECON:
SFR Address: B9H
Function:
Controls access to 640 Bytes
Flash/EE Data Space.
Default:
00H
EADRL:
SFR Address: C6H
Function:
Holds the Flash/EE Data Page
Address. (640 Bytes => 160 Page
Addresses.)
Default:
00H
EDATA 1–4: SFR Address: BCH to BFH respectively
Function:
Holds Flash/EE Data memory
page write or page read data bytes.
Default:
EDATA1–2 –> 00H
EDATA3–4 –> 00H
A block diagram of the SFR interface to the Flash/EE Data
Memory array is shown in Figure 31.
9FH
BYTE 1 BYTE 2 BYTE 3 BYTE 4
00H
EDATA1 (BYTE 1)
EDATA2 (BYTE 2)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
EADRL
ECON COMMAND
INTERPRETER LOGIC
ECON
BYTE 1 BYTE 2 BYTE 3 BYTE 4
FUNCTION:
RECEIVES COMMAND DATA
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
FUNCTION:
HOLDS THE 4-BYTE
PAGE DATA
Figure 31. Flash/EE Data Memory Control and Configuration
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