參數(shù)資料
型號(hào)： ADUC814ARU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 26/72頁(yè)
文件大小： 0K
描述： IC ADC 12BIT W/FLASH MCU 28TSSOP
標(biāo)準(zhǔn)包裝： 50
系列： MicroConverter® ADuC8xx
核心處理器： 8052
芯體尺寸： 8-位
速度： 16.78MHz
連通性： I²C，SPI，UART/USART
外圍設(shè)備： POR，PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 17
程序存儲(chǔ)器容量： 8KB（8K x 8）
程序存儲(chǔ)器類(lèi)型： 閃存
EEPROM 大?。?/td> 640 x 8
RAM 容量： 256 x 8
電壓 - 電源 (Vcc/Vdd)： 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
包裝： 管件
配用： EVAL-ADUC814QSZ-ND - KIT DEV FOR ADUC814 MICROCONVRTR
ADuC814
Rev. A | Page 32 of 72
USING FLASH/EE DATA MEMORY
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH) 4-byte pages as shown in
BYTE 1
9FH
BYTE 2 BYTE 3 BYTE 4
BYTE 1
00H
BYTE 2 BYTE 3 BYTE 4
02748-A
-042
Figure 36. Flash/EE Data Memory Configuration
As with other ADuC814 user-peripheral circuits, the interface
to this memory space is via a group of registers mapped in the
SFR space. EADRL is used to hold the 8-bit address of the page
to be accessed. A group of four data registers (EDATA1–4) is
used to hold 4-byte page data just accessed. Finally, ECON is an
8-bit control register that may be written with one of five
Flash/EE memory access commands to trigger various read,
write, erase, and verify functions. These registers can be
summarized as follows:
ECON
SFR Address
B9H
Function
Controls access to 640 bytes Flash/EE data space.
Default
00H
EADRL
SFR Address
C6H
Function
Holds the Flash/EE data page address.
(640 bytes = > 160 page addresses)
Default
00H
EDATA1–4
SFR Address
BCH to BFH, respectively
Function
Holds Flash/EE data memory page write or page
read data bytes.
Default
EDATA1–4 > 00H
A block diagram of the SFR interface to the Flash/EE data
memory array is shown in Figure 37.
BYTE 1
EADRL
ECON COMMAND
INTERPRETER LOGIC
FUNCTION:
RECEIVES COMMAND DATA
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
FUNCTION:
HOLDS THE 4-BYTE
PAGE DATA
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
ECON
EDATA4 (BYTE 4)
EDATA3 (BYTE 3)
EDATA2 (BYTE 2)
EDATA1 (BYTE 1)
9FH
BYTE 2 BYTE 3 BYTE 4
BYTE 1
00H
BYTE 2 BYTE 3 BYTE 4
02748-A
-043
Figure 37. Flash/EE Data Memory Control and Configuration
ECON—Flash/EE Memory Control SFR
This SFR acts as a command interpreter and may be written
with one of five command modes to enable various read,
program, and erase cycles as detailed in Table 11.
Table 11. ECON–Flash/EE Memory Control Register Command Modes
Command
Byte
Command Mode
Description
01H
READ
Results in 4 bytes being read into EDATA1–4 from memory page address contained in EADRL.
02H
PROGRAM
Results in 4 bytes (EDATA1–4) being written to memory page address in EADRL. This write command
assumes the designated write page has been erased.
03H
Reserved
For internal use. 03H should not be written to the ECON SFR.
04H
VERIFY
Allows the user to verify if data in EDATA1–4 is contained in page address designated by EADRL. A
subsequent read of the ECON SFR results in a zero being read if the verification is valid, a nonzero
value is read to indicate an invalid verification.
05H
ERASE
Results in an erase of the 4-byte page designated in EADRL.
06H
ERASE-ALL
Results in an erase of the full Flash/EE aata memory, 160-page (640 bytes) array.
07H to FFH
Reserved
For future use.
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