參數(shù)資料
型號： ADuC812
廠商： Analog Devices, Inc.
英文描述： 12-Bit ADC with Embedded FLASH MCU(12位8通道A/D轉(zhuǎn)換器)
中文描述： 12位ADC，嵌入式閃存微控制器（12位8通道的A / D轉(zhuǎn)換器）
文件頁數(shù)： 9/31頁
文件大小： 543K
代理商： ADUC812
REV. 0
ADuC812
–
9
–
Table I. ADCCON1 SFR Bit Designations
Bit
Location
Bit
Mnemonic
Description
ADCCON1.7
ADCCON1.6
MD1
MD0
The mode bits (MD1, MD0)
select the active operating mode
of the ADC as follows:
MD1 MD0 Active Mode
0
0
ADC powered down.
0
1
ADC normal mode
1
0
ADC powered down
if not executing a
conversion cycle.
1
1
ADC standby if not
executing a conver-
sion cycle.
ADCCON1.5
ADCCON1.4
CK1
CK0
The ADC clock divide bits (CK1,
CK0) select the divide ratio for
the master clock used to generate
the ADC clock. An ADC con-
version will require 16 ADC
clocks in addition to the selected
number of acquisition clocks (see
AQ0/AQ1 below). The divider
ratio is selected as follows:
CK1
CK0
MCLK Divider
0
0
1
0
1
2
1
0
4
1
1
8
The ADC acquisition select bits
(AQ1, AQ0) select the time avail-
able for the input track/hold
amplifier to acquire the input
signal and is selected as follows:
AQ1
AQ0 #ADC Clks
0
0
1
0
1
2
1
0
3
1
1
4
Note: for analog input source
impedances of <8 k
, the default
AQ0/AQ1 selection of 00, i.e., 1
Acquisition Clock will suffice. For
source impedances greater than
this, it is recommended that you
increase the acquisition clock
selection to 2, 3 or 4 clocks.
The Timer 2 conversion bit (T2C)
is set to enable the Timer 2 over-
flow bit to be used as the ADC
convert start trigger input.
The external trigger enable bit
(EXC) is set to allow the external
Pin 23 (
CONVST
) to be used as
the active low convert start input.
This input should be an active low
pulse (100 ns minimum pulsewidth)
at the required sample rate.
ADCCON1.3
ADCCON1.2
AQ1
AQ0
ADCCON1.1
T2C
ADCCON1.0
EXC
Note: In standby mode the ADC V
REF
circuits are maintained on, while in
powered down mode all ADC peripherals are powered down thus minimizing
current consumption. Typical ADC current consumption is 1.6 mA at V
DD
= 5 V.
provided on-chip. The internal reference may be overdriven via
the external V
REF
pin. This external reference can be in the
range 2.3 V to AV
DD
.
Single step or continuous conversion modes can be initiated in
software or, alternatively, by applying a convert signal to an
external Pin 25 (
CONVST
). Timer 2 can also be configured
to generate a repetitive trigger for ADC conversions. The ADC
may be configured to operate in a DMA Mode whereby the
ADC block continuously converts and captures samples to an
external RAM space without any interaction from the MCU
core. This automatic capture facility can extend through a
16 MByte external Data Memory space.
The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal Offset and Gain calibration registers, a
software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
users target system.
A voltage output from an on-chip temperature sensor propor-
tional to absolute temperature can also be routed through the
front-end ADC multiplexor (effectively a 9th ADC channel
input) facilitating a temperature sensor implementation.
ADC Transfer Function
The analog input range for the ADC is 0 V to V
REF
. For this
range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when
V
REF
= 2.5 V. The ideal input/output transfer characteristic for
the 0 to V
REF
range is shown in Figure 4.
OUTPUT
CODE
111...111
111...110
111...101
111...100
000...011
000...010
000...001
000...000
0V
1LSB
+FS
–
1LSB
VOLTAGE INPUT
1LSB =
FS
4096
Figure 4. ADuC812 ADC Transfer Function
SFR Interface to ADC Block
The ADC operation is fully controlled via three SFRs, namely:
ADCCON1 – (ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
EFH
20H
NO
MD1
MD0
CK1
CK0
AQ1
AQ0
T2C
EXC
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