參數(shù)資料
型號(hào)： ADuC812
廠商： Analog Devices, Inc.
英文描述： 12-Bit ADC with Embedded FLASH MCU(12位8通道A/D轉(zhuǎn)換器)
中文描述： 12位ADC，嵌入式閃存微控制器（12位8通道的A / D轉(zhuǎn)換器）
文件頁數(shù)： 12/31頁
文件大?。?/td> 543K
代理商： ADUC812
REV. 0
ADuC812
–
12
–
In normal mode of operation each DAC is updated when the
low DAC nibble (DACxL) SFR is written. Both DACs can be
updated simultaneously using the SYNC bit in the DACCON
SFR.
In 8-bit mode of operation, the 8-bit byte written to the DACxL
registers is automatically routed to the top 8 bits of each 12-bit
DAC. The bit designations of the DACCON SFR are shown
below in Table IV.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
FDH
04H
NO
MODE RNG1 RNG0 CLR1 CLR0
SYNC PD1 PD0
Table IV. DACCON SFR Bit Designations
Bit
Location
Bit
Mnemonic
Description
DACCON.7
MODE
The DAC MODE bit sets the
overriding operating mode for
both DACs.
Set to “1” = 8-bit mode (Write 8
bits to DACxL SFR.
Set to “0” = 12-bit mode.
DAC1 range select bit.
Set to “1” = DAC1 range 0–V
DD
.
Set to “0” = DAC1 range 0–V
REF
.
DAC0 range select bit.
Set to “1” = DAC0 range 0–V
DD
.
Set to “0” = DAC0 range 0–V
REF
.
DAC1 clear bit.
Set to “0” = DAC1 output forced
to 0 V.
Set to “1” = DAC1 output
normal.
DAC0 clear bit.
Set to “0” = DAC0 output forced
to 0 V.
Set to “1” = DAC0 output normal.
DAC0/1 update synchronization
bit.
When set to “1” the DAC outputs
update as soon as the DACxL
SFRs are written.
The user can simultaneously up-
date both DACs by first updating
the DACxL/H SFRs while SYNC
is “0.”
Both DACs will then update
simultaneously when the SYNC
bit is set to “1.”
DAC1 Power-Down Bit.
Set to “1” = Power-On DAC1.
Set to “0” = Power-Off DAC1.
DAC0 Power-Down Bit.
Set to “1” = Power-On DAC0.
Set to “0” = Power-Off DAC0.
DACCON.6
RNG1
DACCON.5
RNG0
DACCON.4
CLR1
DACCON.3
CLR0
DACCON.2
SYNC
DACCON.1
PD1
DACCON.0
PD0
NONVOLATILE FLASH MEMORY
Flash Memory Overview
The ADuC812 incorporates Flash memory technology on-chip
to provide the user with a nonvolatile, in-circuit reprogram-
mable, code and data memory space.
Flash memory is the newest type of nonvolatile memory
technology and is based on a single transistor cell architecture.
This technology is basically an outgrowth of EPROM
technology and was developed through the late 1980s.
Flash memory takes the flexible in-circuit reprogrammable
features of EEPROM and combines them with the space
efficient/density features of EPROM (see Figure 8).
Because Flash technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must be erased first; the erase being
performed in sector blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
FLASH/EE MEMORY
TECHNOLOGY
SPACE EFFICIENT/
DENSITY
IN-CIRCUIT
REPROGRAMMABLE
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
Figure 8. Flash Memory Development
Overall, Flash/EE memory represents a step closer towards
the ideal memory device that includes nonvolatility, in-circuit
programmability, high density and low cost. Incorporated in
the ADuC812, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
Flash/EE Memory and the ADuC812
The ADuC812 provides two arrays of Flash/EE memory for
user applications.
8K bytes of Flash/EE Program space are provided on-chip to
facilitate code execution without any external discrete ROM
device requirements. The program memory can be programmed
using conventional third party memory programmers. This array
can also be programmed in-circuit, using the serial download
mode provided.
A 640-Byte Flash/EE Data Memory space is also provided on-
chip. This may be used by the user as a general purpose non-
volatile scratchpad area. User access to this area is via a group of
six SFRs. This space can be programmed at a byte level, al-
though it must first be erased in 4-byte sectors.
Using the Flash/EE Program Memory
This 8K Byte Flash/EE Program Memory array is mapped
into the lower 8K bytes of the 64K bytes program space ad-
dressable by the ADuC812 and will be used to hold user code
in typical applications.
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