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| 型號(hào)： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 57/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 60 of 92
Table 82. COMxIEN0 MMR Bit Designations
Bit
Name
Description
7:4
RSVD
Reserved.
3
EDSSI
Modem Status Interrupt Enable Bit.
Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set.
Cleared by user.
2
ELSI
RX Status Interrupt Enable Bit.
Set by user to enable generation of an interrupt if any of COMxSTA0[3:1] are set.
Cleared by user.
1
ETBEI
Enable Transmit Buffer Empty Interrupt.
Set by user to enable interrupt when buffer is empty during a transmission.
Cleared by user.
0
ERBFI
Enable Receive Buffer Full Interrupt.
Set by user to enable interrupt when buffer is full during a reception.
Cleared by user.
Table 83. COMxIID0 MMR Bit Designations
Bit 2:1
Status Bits
Bit 0
NINT
Priority
Definition
Clearing Operation
00
1
No Interrupt.
11
0
1
Receive Line Status Interrupt.
Read COMxSTA0.
10
0
2
Receive Buffer Full Interrupt.
Read COMxRX.
01
0
3
Transmit Buffer Empty Interrupt.
Write data to COMxTX or read COMxIID0.
00
0
4
Modem Status Interrupt.
Read COMxSTA1.
Table 84. COMxCON1 MMR Bit Designations
Bit
Name
Description
7:5
RSVD
Reserved.
4
LOOPBACK
Loop Back.
Set by user to enable loop-back mode. In loop-back mode, the SOUT is forced high. In addition, the modem
signals are directly connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2 to DCD).
3
Reserved.
2
Reserved.
1
RTS
Request to Send.
Set by user to force the RTS output to 0.
Cleared by user to force the RTS output to 1.
0
DTR
Data Terminal Ready.
Set by user to force the DTR output to 0.
Cleared by user to force the DTR output to 1.
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