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參數(shù)資料
| 型號(hào)： | ADUC7129BSTZ126-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 38/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS MCU ARM7 ADC/DDS 80-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control Direct Digital Synthesis Tutorial Series (1 of 7): Introduction |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 41.78MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設(shè)備： | PLA，POR，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲(chǔ)器容量： | 126KB（63K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 10x12b; D/A 1x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADUC7129BSTZ126-RLDKR |
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ADuC7128/ADuC7129
Rev. 0 | Page 43 of 92
Table 44. FEE0PRO and FEE0HID MMR Bit Designations
Bit
Description
31
Read Protection.
Cleared by user to protect Block 0.
Set by user to allow reading Block 0.
30:0
Write Protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 3 to Page 0.
Cleared by user to protect the pages in writing.
Set by user to allow writing the pages.
Table 45. FEE1PRO and FEE1HID MMR Bit Designations
Bit
Description
31
Read Protection.
Cleared by user to protect Block 1.
Set by user to allow reading Block 1.
30
Write Protection for Page 127 to Page 120.
Cleared by user to protect the pages in writing.
Set by user to allow writing the pages.
31:0
Write Protection for Page 119 to Page 116 and for Page 3 to Page 0.
Cleared by user to protect the pages in writing.
Set by user to allow writing the pages.
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns and a clock cycle is 22 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE), one
cycle to execute the instruction and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction, such as a branch
instruction, takes one cycle to fetch, but it also takes two cycles
to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 23 ns, execution from Flash/EE cannot be done in one
cycle (as can be done from SRAM when the CD bit = 0). In addi-
tion, some dead times are needed before accessing data for any
value of CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In Thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruction
to be executed is a control flow instruction, an extra cycle is
needed to decode the new address of the program counter and
then four cycles are needed to fill the pipeline. A data processing
instruction involving only core registers doesn’t require any
extra clock cycles, but if it involves data in Flash/EE, an extra
clock cycle is needed to decode the address of the data and two
cycles to get the 32-bit data from Flash/EE. An extra cycle must
also be added before fetching another instruction. Data transfer
instructions are more complex and are summarized in Table 46.
Table 46. Execution Cycles in ARM/Thumb Mode
Instructions
Fetch
Cycles
Dead
Time
Data Access
Dead
Time
LD
2/1
1
2
1
LDH
2/1
1
LDM/PUSH
2/1
N
2 × N
N
STR
2/1
1
2 × 20 μs
1
STRH
2/1
1
20 μs
1
STRM/POP
2/1
N
2 × N × 20 μs
N
With 1 < N ≤ 16, N is the number of bytes of data to load or
store in the multiple load/store instruction. The SWAP instruction
combines an LD and STR instruction with only one fetch,
giving a total of eight cycles plus 40 μs.
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