參數(shù)資料
型號： ADUC7036BCPZ
廠商： Analog Devices Inc
文件頁數(shù)： 90/132頁
文件大?。?/td> 0K
描述： IC MCU FLASH 96K ANLGI/O 48LFCSP
產(chǎn)品培訓模塊： Process Control
標準包裝： 1
系列： MicroConverter® ADuC7xxx
核心處理器： ARM7
芯體尺寸： 16/32-位
速度： 20.48MHz
連通性： LIN，SPI，UART/USART
外圍設(shè)備： PSM，溫度傳感器，WDT
輸入/輸出數(shù)： 9
程序存儲器容量： 96KB（48K x 16）
程序存儲器類型： 閃存
RAM 容量： 1.5K x 32
電壓 - 電源 (Vcc/Vdd)： 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 2x16b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 115°C
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
包裝： 托盤
ADuC7036
Rev. C | Page 60 of 132
For the current channel ADC,
The offset coefficient is read from the ADC0OF calibration
register and is a 16-bit, twos complement number. The range of
this number, in terms of the signal chain, is effectively ±1.
Therefore, 1 LSB of the ADC0OF register is not the same as
1 LSB of the ADC0DAT register.
NOM
REF
IN
OUT
ADCxGN
ADCxOF
K
V
PGA
V
ADC
×
=
×
where K is dependent on the PGA gain setting and ADC mode.
A positive value of ADC0OF indicates that when offset is
subtracted from the output of the filter, a negative value is added.
The nominal value of this register is 0x0000, indicating zero
offset is to be removed. The actual offset of the ADC can vary
slightly from part to part and at different PGA gains. The offset
within the ADC is minimized if the chopping mode is enabled
(that is, ADCFLT[15] = 1).
Normal Mode
In normal mode, K = 1 for PGA gains of 1, 4, 8, 16, 32, and 64;
K = 2 for PGA gains of 2 and 128; K = 4 for a PGA gain of 256;
and K = 8 for a PGA gain of 512.
Low Power Mode
In low power mode, K = 32 for a PGA gain of 128. In addition,
if the REG_AVDD/2 reference is used, the K factor doubles.
The gain coefficient is read from the ADC0GN register and is a
unitless scaling factor. The 16-bit value in this register is divided
by 16,384 and then multiplied by the offset-corrected value. The
nominal value of this register equals 0x5555, corresponding to a
multiplication factor of 1.3333, and scales the nominal ±0.75 signal
to produce a full-scale output signal of ±1. The resulting output
signal is checked for overflow/underflow and converted to twos
complement or unipolar mode before being output to the data
register.
Low Power Plus Mode
In low power plus mode, K = 8 for a PGA gain of 512. In addition,
if the REG_AVDD/2 reference is used, the K factor doubles.
ADC DIAGNOSTICS
The ADuC7036 features a diagnostic capability and open-
circuit detection on both ADCs.
Current ADC Diagnostics
The actual gain and the required scaling coefficient for zero
gain error vary slightly from part to part at different PGA set-
tings in normal and low power modes. The value downloaded into
ADC0GN during a power-on reset represents the scaling factor
for a PGA gain of 1. If a different PGA setting is used, however,
some gain error may be present. To correct this error, overwrite
the calibration coefficients via user code or perform an ADC
calibration.
The ADuC7036 features the capability to detect open-circuit
conditions on the current channel inputs. This is accomplished
using the two current sources on IIN+ and IIN, which are
controlled via ADC0CON[14:13].
Note that the IIN+ and IIN current sources have a tolerance of
±30%. Therefore, a PGA gain ≥ 2 (ADC0CON[3:0] ≥ 0001) must
be used when current sources are enabled.
The simplified ADC transfer function can be described as
Temperature ADC Diagnostics
The ADuC7036 features the capability to detect open-circuit
conditions on the temperature channel inputs. This is
accomplished using the two current sources on VTEMP and
GND_SW, which are controlled via ADC1CON[14:13].
NOM
REF
IN
OUT
ADCxGN
ADCxOF
V
PGA
V
ADC
×
×
=
where the equation is valid for the voltage/temperature chan-
nel ADC.
Voltage ADC Diagnostics
The ADuC7036 features the capability to detect open-circuit
conditions on the voltage channel input. This is accomplished
using the current source on the voltage attenuator, controlled by
the high voltage register HVCFG1[7].
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