參數(shù)資料
型號: ADUC7036BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 53/132頁
文件大?。?/td> 0K
描述: IC MCU FLASH 96K ANLGI/O 48LFCSP
產(chǎn)品培訓模塊: Process Control
標準包裝: 1
系列: MicroConverter® ADuC7xxx
核心處理器: ARM7
芯體尺寸: 16/32-位
速度: 20.48MHz
連通性: LIN,SPI,UART/USART
外圍設備: PSM,溫度傳感器,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
RAM 容量: 1.5K x 32
電壓 - 電源 (Vcc/Vdd): 3.5 V ~ 18 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 2x16b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 115°C
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
包裝: 托盤
ADuC7036
Rev. C | Page 27 of 132
Command Sequence for Executing a Mass Erase
Given the significance of the mass erase command, the following
specific code sequence must be executed to initiate this
operation:
Set Bit 3 in FEExMOD.
Write 0xFFC3 in FEExADR.
Write 0x3CFF in FEExDAT.
Run the mass erase command (Code 0x06) in FEExCON.
This sequence is illustrated by the following example:
Int a = FEExSTA;
// Ensure FEExSTA is
cleared
FEExMOD = 0x08
FEExADR = 0xFFC3
FEExDAT = 0x3CFF
FEExCON = 0x06;
// Mass erase command
while (FEExSTA & 0x04){} //Wait for command
to finish
It should be noted that to run the mass erase command via
FEE0CON, the write protection on the lower 64 kB must be
disabled. That is, FEE1HID/FEE1PRO are set to 0xFFFFFFFF.
This setting can be accomplished by first removing the protec-
tion or by erasing the lower 64 kB.
FEE0STA and FEE1STA Registers
Name: FEE0STA and FEE1STA
Address: 0xFFFF0E00 and 0xFFFF0E80
Default Value: 0x20
Access: Read only
Function: These 8-bit, read only registers can be read by user
code, and they reflect the current status of the Flash/EE
memory controllers.
Table 14. FEE0STA and FEE1STA MMR Bit Designations
Bit
7 to 4
Not used. These bits are not used and always read as 0.
3
Flash/EE interrupt status bit.
Set automatically when an interrupt occurs, that is,
when a command is complete and the Flash/EE
interrupt enable bit in the FEExMOD register is set.
Cleared automatically when the FEExSTA register is read
by user code.
2
Flash/EE controller busy.
Set automatically when the Flash/EE controller is busy.
Cleared automatically when the controller is not busy.
1
Command fail.
Set automatically when a command written to FEExCON
completes unsuccessfully.
Cleared automatically when the FEExSTA register is read
by user code.
0
Command successful.
Set automatically by the MCU when a command is
completed successfully.
Cleared automatically when the FEE0STA register is read
by user code.
1 The x represents 0 or 1, designating Flash/EE Block 0 or Flash/EE Block 1.
FEE0ADR and FEE1ADR Registers
Name: FEE0ADR and FEE1ADR
Address: 0xFFFF0E10 and 0xFFFF0E90
Default Value: 0x0000 (FEE1ADR). For FEE0ADR, see the
Access: Read/write access
Function: These 16-bit registers dictate the address acted upon
when a Flash/EE command is executed via FEExCON.
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