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參數(shù)資料
| 型號： | ADUC7026BSTZ62I |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 79/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU FLASH 62K ANLG I/0 80LQFP |
| 產(chǎn)品培訓模塊： | ARM7 Applications & Tools Intro to ARM7 Core & Microconverters Process Control |
| 標準包裝： | 1 |
| 系列： | MicroConverter® ADuC7xxx |
| 核心處理器： | ARM7 |
| 芯體尺寸： | 16/32-位 |
| 速度： | 44MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | PLA，PWM，PSM，溫度傳感器，WDT |
| 輸入/輸出數(shù)： | 40 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 32 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12 x12b; D/A 4x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 80-LQFP |
| 包裝： | 托盤 |
| 配用： | EVAL-ADUC7026QSPZ-ND - KIT DEV ADUC7026/7027 QUICK PLUS EVAL-ADUC7026QSZ-ND - KIT DEV FOR ADUC7026/7027 |
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ADuC7019/20/21/22/24/25/26/27/28/29
Data Sheet
Rev. F | Page 76 of 104
I2C-COMPATIBLE INTERFACES
The ADuC7019/20/21/22/24/25/26/27/28/29 support two licensed
I2C interfaces. The I2C interfaces are both implemented as a hard-
ware master and a full slave interface. Because the two I2C inter-
faces are identical, this data sheet describes only I2C0 in detail.
Note that the two masters and one of the slaves have individual
interrupts (see the Interrupt System section).
Note that when configured as an I2C master device, the
ADuC7019/20/21/22/24/25/26/27/28/29 cannot generate a
repeated start condition.
The two GPIO pins used for data transfer, SDAx and SCLx, are
configured in a wired-AND format that allows arbitration in a
multimaster system. These pins require external pull-up resistors.
Typical pull-up values are 10 k.
The I2C bus peripheral address in the I2C bus system is pro-
grammed by the user. This ID can be modified any time a
transfer is not in progress. The user can configure the interface
to respond to four slave addresses.
The transfer sequence of an I2C system consists of a master
device initiating a transfer by generating a start condition while
the bus is idle. The master transmits the slave device address
and the direction of the data transfer during the initial address
transfer. If the master does not lose arbitration and the slave
acknowledges, the data transfer is initiated. This continues until
the master issues a stop condition and the bus becomes idle.
The I2C peripheral can be configured only as a master or slave
at any given time. The same I2C channel cannot simultaneously
support master and slave modes.
Serial Clock Generation
The I2C master in the system generates the serial clock for a
transfer. The master channel can be configured to operate in
fast mode (400 kHz) or standard mode (100 kHz).
The bit rate is defined in the I2C0DIV MMR as follows:
)
(2
)
2
(
DIVL
DIVH
+
=
UCLK
CLOCK
SERIAL
f
where:
fUCLK = clock before the clock divider.
DIVH = the high period of the clock.
DIVL = the low period of the clock.
Thus, for 100 kHz operation,
DIVH = DIVL = 0xCF
and for 400 kHz,
DIVH = 0x28, DIVL = 0x3C
The I2CxDIV registers correspond to DIVH:DIVL.
Slave Addresses
The registers I2C0ID0, I2C0ID1, I2C0ID2, and I2C0ID3 contain
the device IDs. The device compares the four I2C0IDx registers
to the address byte. To be correctly addressed, the seven MSBs of
either ID register must be identical to that of the seven MSBs of
the first received address byte. The LSB of the ID registers (the
transfer direction bit) is ignored in the process of address
recognition.
I2C Registers
The I2C peripheral interface consists of 18 MMRs, which are
discussed in this section.
Table 126. I2CxMSTA Registers
Name
Address
Default Value
Access
I2C0MSTA
0xFFFF0800
0x00
R/W
I2C1MSTA
0xFFFF0900
0x00
R/W
I2CxMSTA are status registers for the master channel.
Table 127. I2C0MSTA MMR Bit Descriptions
Bit
Access
Type
Description
7
R/W
Master transmit FIFO flush. Set by user to flush
the master Tx FIFO. Cleared automatically after
the master Tx FIFO is flushed. This bit also
flushes the slave receive FIFO.
6
R
Master busy. Set automatically if the master is
busy. Cleared automatically.
5
R
Arbitration loss. Set in multimaster mode if
another master has the bus. Cleared when the
bus becomes available.
4
R
No ACK. Set automatically if there is no
acknowledge of the address by the slave
device. Cleared automatically by reading the
I2C0MSTA register.
3
R
Master receive IRQ. Set after receiving data.
Cleared automatically by reading the I2C0MRX
register.
2
R
Master transmit IRQ. Set at the end of a
transmission. Cleared automatically by writing
to the I2C0MTX register.
1
R
Master transmit FIFO underflow. Set
automatically if the master transmit FIFO is
underflowing. Cleared automatically by
writing to the I2C0MTX register.
0
R
Master TX FIFO not full. Set automatically if the
slave transmit FIFO is not full. Cleared automati-
cally by writing twice to the I2C0STX register.
Table 128. I2CxSSTA Registers
Name
Address
Default Value
Access
I2C0SSTA
0xFFFF0804
0x01
R
I2C1SSTA
0xFFFF0904
0x01
R
I2CxSSTA are status registers for the slave channel.
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