參數資料
型號: ADT7411ARQ-REEL
廠商: Analog Devices, Inc.
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:26; Series:LJT07R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:17; Circular Contact Gender:Pin; Circular Shell Style:Jam Nut Receptacle; Insert Arrangement:17-26
中文描述: SPI/I2C兼容,10位數字溫度傳感器和8通道ADC
文件頁數: 4/36頁
文件大?。?/td> 456K
代理商: ADT7411ARQ-REEL
ADT7411
Parameter
1
ROUND ROBIN UPDATE RATE
2
Rev. A | Page 4 of 36
Min
Typ
Max
Unit
Conditions/Comments
Time to complete one measurement cycle through all
channels.
AIN1 and AIN2 are selected on Pins 7 and 8.
AIN1 and AIN2 are selected on Pins 7 and 8.
D+ and D– are selected on Pins 7 and 8.
D+ and D are selected on Pins 7 and 8.
AIN1 and AIN2 are selected on Pins 7 and 8.
AIN1 and AIN2 are selected on pins 7 and 8.
D+ and D are selected on Pins 7 and 8.
D+ and D are selected on Pins 7 and 8.
V
IN
= 0 V to V
DD
.
All Digital Inputs.
Input filtering suppresses noise spikes of less than 50 ns.
I
SOURCE
= I
SINK
= 200 μA.
I
OL
= 3 mA.
V
OH
= 5 V.
I
OUT
= 4 mA.
Fast-Mode I
2
C. See Figure 2.
See Figure 2.
See Figure 2.
See Figure 2.
See Figure 2.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
See Figure 3.
Slow ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
Fast ADC @ 25°C
Averaging On
Averaging Off
Averaging On
Averaging Off
ON-CHIP REFERENCE
3
Reference Voltage
Temperature Coefficient
DIGITAL INPUTS
1, 3
Input Current
V
IL
, Input Low Voltage
V
IH
, Input High Voltage
Pin Capacitance
SCL, SDA Glitch Rejection
DIGITAL OUTPUT
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output High Current, I
OH
Output Capacitance, C
OUT
INT/INT Output Saturation Voltage
I
2
C TIMING CHARACTERISTICS
4, 5
Serial Clock Period, t
1
Data In Setup Time to SCL High, t
2
Data Out Stable after SCL Low, t
3
SDA Low Setup Time to SCL Low
(Start Condition), t
4
SDA High Hold Time after SCL High
(Stop Condition), t
5
SDA and SCL Fall Time, t
6
SPI TIMING CHARACTERISTICS
1, 3, 6
CS to SCLK Setup Time, t
1
SCLK High Pulse Width, t
2
SCLK Low Pulse Width, t
3
Data Access Time after SCLK
Falling Edge, t
4 6
Data Setup Time Prior to SCLK
Rising Edge, t
5
Data Hold Time after SCLK
Rising Edge, t
6
1.89
2.4
2.5
50
0
50
50
0
50
50
20
0
125.4
17.1
140.36
12.11
9.26
578.96
24.62
3.25
2.25
80
3
±1
0.8
10
50
0.4
1
50
0.8
90
35
ms
ms
ms
ms
ms
μs
ms
ms
V
ppm/°C
μA
V
V
pF
ns
V
V
mA
pF
V
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
Round robin is the continuous sequential measurement of the following channels: V
DD
, internal temperature, external temperature (AIN1, AIN2), AIN3, AIN4, AIN5,
AIN6, AIN7, and AIN8.
3
Guaranteed by design and characterization, not production tested.
4
The SDA and SCL timing is measured with the input filters turned on so as to meet the FAST-Mode I
2
C specification. Switching off the input filters improves the transfer
rate, but has a negative effect on the EMC behavior of the part.
5
Guaranteed by design. Not tested in production.
6
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
), and timed from a voltage level of 1.6 V.
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