參數(shù)資料
型號(hào)： ADT7318ARU
廠商： ANALOG DEVICES INC
元件分類： 溫度/濕度傳感器
英文描述： DIGITAL TEMP SENSOR-SERIAL, 8BIT(s), 3Cel, RECTANGULAR, SURFACE MOUNT
封裝： QSOP-16
文件頁(yè)數(shù)： 4/24頁(yè)
文件大?。?/td> 279K
代理商： ADT7318ARU
–12–
REV. PrH
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
FUNCTIONAL DESCRIPTION - DAC
The ADT7316/7317/7318 has quad resistor-string DACs
fabricated on a CMOS process with a resolutions of 12,
10 and 8 bits respectively. They contain four output buffer
amplifiers and is written to via I
2C serial interface or SPI
serial interface. Selection between the two types of inter-
face is done on the first valid serial communication. If the
first valid serial communication to the part is I
2C then the
internal interface circuit will be locked to I
2C communica-
tion. The same holds for SPI interfacing.
The ADT7316/7317/7318 operates from a single supply
of 2.5 V to 5.5 V and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7V/
s.
DACs A and B share a common reference input, namely
VREFAB. DACs C and D share a common reference input,
namely VREFCD. Each reference input may be buffered to
draw virtually no current from the reference source, or
unbuffered to give a reference input range from GND to
VDD. The devices have a power-down mode, in which all
DACs may be turned off completely with a high-imped-
ance output.
Digital-to-Analog Section
The architecture of one DAC channel consists of a resis-
tor-string DAC followed by an output buffer amplifier.
The voltage at the VREF pin provides the reference voltage
for the corresponding DAC. Figure 4 shows a block dia-
gram of the DAC architecture. Since the input coding to
the DAC is straight binary, the ideal output voltage is
given by:
VREF * D
VOUT = ----------
2
N
where D=decimal equivalent of the binary code which is
loaded to the DAC register;
0-255 for ADT7318 (8-Bits)
0-1023 for ADT7317 (10-Bits)
0-4095 for ADT7316 (12-Bits)
N = DAC resolution.
RESISTOR
STRING
BU.
VRE.AB
OUTPUT BU..ER
AMPLI.IER
RE.ERENCE
BU..ER
DAC
REGISTER
VOUTA
GAIN MODE
(GAIN= 1 or 2)
INPUT
REGISTER
Figure 4. Single DAC channel architecture
Resistor String
The resistor string section is shown in Figure 5. It is sim-
ply a string of resistors, each of value R. The digital code
loaded to the DAC register determines at what node on
the string the voltage is tapped off to be fed into the out-
put amplifier. The voltage is tapped off by closing one of
the switches connecting the string to the amplifier. Be-
cause it is a string of resistors, it is guaranteed monotonic.
DAC Reference Inputs
There is a reference pin for each pair of DACs. The refer-
ence inputs are buffered but can also be individually con-
figured as unbuffered. The advantage with the buffered
input is the high impedance it presents to the voltage
source driving it. However if the unbuffered mode is used,
the user can have a reference voltage as low as 0.25 V and
as high as VDD since there is no restriction due to head-
room and footroom of the reference amplifier.
R
TO OUTPUT
AMPLI.IER
Figure 5. Resistor String
If there is a buffered reference in the circuit , there is no
need to use the on-chip buffers. In unbuffered mode the
input impedance is still large at typically 90 k
per refer-
ence input for 0-VREF mode and 45 k
for 0-2V
REF mode.
The buffered/unbuffered option is controlled by the con-
figuration register (see data register descriptions).
There is also an option to use the internal temperature
reference. This option is controlled by the configuration
register.
Output Amplifier
The output buffer amplifier is capable of generating out-
put voltages to within 1mV of either rail. Its actual range
depends on the value of VREF, GAIN and offset error.
If a gain of 1 is selected (GAIN=0) the output range is
0.001 V to VREF.
If a gain of 2 is selected (GAIN=1) the output range is
0.001 V to 2VREF. However because of clamping the maxi-
mum output is limited to VDD - 0.001V.
The output amplifier is capable of driving a load of 2k
to GND or VDD, in parallel with 500pF to GND or VDD.
The source and sink capabilities of the output amplifier
can be seen in the plot in TPC tbd.
The slew rate is 0.7V/
s with a half-scale settling time to
+/-0.5 LSB (at 8 bits) of 6
s.
FUNCTIONAL DESCRIPTION - Temperature Sensor
The ADT7316/7317/7318 contains a two-channel A to D
converter with special input signal conditioning to enable
operation with external and on-chip diode temperature
sensors. When the ADT7316/7317/7318 is operating nor-
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