
–6–
REV. PrH
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
ADT7316/7317/7318
ADT7318 PIN .UNCTION DESCRIPTION
Pin
Mnemonic
Description
1VOUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
2VOUTA
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
3VREFAB
Reference Input Pin for DACs A and B.It may be configured as a buffered or unbuffered input
to each or both of the DACs A and B. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
4
CS
SPI Active low control Input. This is the frame synchronization signal for the input data.
When CS
goes low, it enables the input register and data is transferred in on the rising edges
of the following serial clocks and transferred out on the falling edges.
5
G N D
Ground Reference Point for All Circuitry on the part. Analog and Digital Ground.
6VDD
Positive Supply Voltage, +2.65 V to +5.25 V.The supply should be decoupled to ground.
7
D +
Positive connection to external temperature sensor
8
D -
Negative connection to external temperature sensor
9
ALERT/OTI
ALERT - SMBus Alert. Open-Drain output. Over temperature indicator, becomes active low
when temperature exceeds either internal or external temperature high limits.
OTI - SPI Temperature Indicator. The output polarity of this pin can be set to give an active
low or active high interrupt when temperature high limits are exceeded.
10
LDAC
Active low control input that transfers the contents of the input registers to their respective
DAC registers. Pulsing this pin low allows any or all DAC registers to be updated if the input
registers have new data. This allows simultaneous update of all DAC outputs. Alternatively
this pin can be tied permanently low.
11
DOUT/ADD
SPI Serial Data Output. Logic Output. Data is clocked out of any register at this pin. Data is
clocked out at the falling edge of SCLK.
ADD, I
2C serial bus address selection pin. Logic input. During the first valid I2C bus commu-
nication this pin is checked to determine the serial bus address assigned to the ADT7316/17/
18. Any subsequent changes on this pin will have no affect on the I2C serial bus address. A low
on this pin gives the address 1001 000, leaving it floating gives the address 1001 001 and set-
ting it high gives the address 1001 010.
12
SDA/DIN
SDA - I
2C Serial Data Input. I2C serial data to be loaded into the parts registers is provided
on this input.
DIN - SPI Serial Data Input. Serial data to be loaded into the parts registers is provided on
this input. Data is clocked into a register on the rising edge of SCLK.
13
SCL/SCLK
Serial Clock Input. This is the clock input for the serial port. The serial clock is used to clock
data out of any register of the ADT7316/7317/7318 and also to clock data into any register
that can be written to.
14
VREFCD
Reference Input Pin for DACs C and D.It may be configured as a buffered or unbuffered input
to each or both of the DACs C and D. It has an input range from 0.25 V to VDD in unbuffered
mode and from 1 V to VDD in buffered mode.
15
VOUTD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
16
VOUTC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.