參數(shù)資料
型號(hào)： ADSP-TS202SABP-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號(hào)處理
英文描述： TigerSHARC Embedded Processor
中文描述： 64-BIT, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù)： 34/40頁
文件大小： 615K
代理商： ADSP-TS202SABP-X
Rev. PrB
|
Page 34 of 40
|
December 2003
ADSP-TS202S
Preliminary Technical Data
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to when they start driv-
ing. The time for the voltage on the bus to ramp by
V is
dependent on the capacitive load, C
L
, and the drive current, I
D
.
This ramp time can be approximated by the following equation:
The output enable time t
ENA
is the difference between
t
MEASURED_ENA
and t
RAMP
as shown in
Figure 32
. The time
t
MEASURED_ENA
is the interval from when the reference signal
switches to when the output voltage ramps
V from the mea-
sured three-stated output level. t
RAMP
is calculated with test load
C
L
, drive current I
D
, and with
V equal to 0.4 V.
Capacitive Loading
Output valid and hold are based on standard capacitive loads:
30 pF on all pins (see
Figure 33
). The delay and hold specifica-
tions given should be derated by a drive strength related factor
for loads other than the nominal value of 30 pF.
Figure 34
through
Figure 41
show how output rise time varies with capac-
itance.
Figure 42
graphically shows how output valid varies with
load capacitance. (Note that this graph or derating does not
apply to output disable delays; see
Output Disable Time on
page 33
.) The graphs of
Figure 34
through
Figure 42
may not be
linear outside the ranges shown.
Figure 33. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 34. Typical Output Rise and Fall Time (10%–90%, V
DD_IO
=2.5V) vs.
Load Capacitance at Strength0
tRAMP
CLV
(
)
ID
=
1.25V
TO
OUTPUT
PIN
30pF
50
STRENGTH 0
(V
DD_IO
= 2.5V)
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
R
LOAD CAPACITANCE – pF
RISE TIME
y = 0.2015x + 3.8869
FALL TIME
y = 0.174x + 2.6931
PRELMNARY
Figure 35. Typical Output Rise and Fall Time (10%–90%, V
DD_IO
=2.5V) vs.
Load Capacitance at Strength1
Figure 36. Typical Output Rise and Fall Time (10%–90%, V
DD_IO
=2.5V) vs.
Load Capacitance at Strength2
Figure 37. Typical Output Rise and Fall Time (10%–90%, V
DD_IO
=2.5V) vs.
Load Capacitance at Strength3
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
R
LOAD CAPACITANCE – pF
RISE TIME
y = 0.1349x + 1.9955
FALL TIME
y = 0.1163x + 1.4058
STRENGTH 1
(V
DD_IO
= 2.5V)
PRELIMINARY
0
10
20
30
LOAD CAPACITANCE – pF
40
50
60
70
80
90
100
0
5
10
15
20
25
R
RISE TIME
y = 0.1304x + 0.8427
FALL TIME
y = 0.1144x + 0.7025
STRENGTH 2
(V
DD_IO
= 2.5V)
PRELMNARY
0
10
20
30
40
50
60
70
80
90
100
0
5
10
15
20
25
R
LOAD CAPACITANCE – pF
RISE TIME
y = 0.1082x + 1.3123
FALL TIME
y = 0.0912x + 1.2048
STRENGTH 3
(V
DD_IO
= 2.5V)
PRELMNARY
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