參數(shù)資料
型號： ADSP-TS202SABP-X
廠商： ANALOG DEVICES INC
元件分類： 數(shù)字信號處理
英文描述： TigerSHARC Embedded Processor
中文描述： 64-BIT, OTHER DSP, PBGA576
封裝： 25 X 25 MM, MS-034, EBGA-576
文件頁數(shù)： 14/40頁
文件大?。?/td> 615K
代理商： ADSP-TS202SABP-X
Rev. PrB
|
Page 14 of 40
|
December 2003
ADSP-TS202S
Preliminary Technical Data
Table 6. Pin Definitions—External Port Arbitration
Signal
BR7–0
Type
I/O
Term
V
DD_IO
Description
Multiprocessing Bus Request Pins. Used by the DSPs in a multiprocessor system to
arbitrate for bus mastership. Each DSP drives its own BRx line (corresponding to the
value of its ID2–0 inputs) and monitors all others. In systems with fewer than eight
DSPs, set the unused BRx pins high (V
DD_IO
).
Multiprocessor ID. Indicates the DSP’s ID, from which the DSP determines its order in
a multiprocessor system. These pins also indicate to the DSP which bus request
(BR0–BR7) to assert when requesting the bus: 000 = BR0, 001 = BR1, 010 = BR2,
011 = BR3, 100 = BR4, 101 = BR5, 110 = BR6, or 111 = BR7. ID2–0 must have a constant
value during system operation and can change during reset only.
Bus Master. The current bus master DSP asserts BM. For debugging only. At reset this
is a strap pin. For more information, see
Table 15 on page 19
.
Back Off. A deadlock situation can occur when the host and a DSP try to read from
each other’s bus at the same time. When deadlock occurs, the host can assert BOFF
to force the DSP to relinquish the bus before completing its outstanding transaction.
Bus Lock Indication. Provides an indication that the current bus master has locked
the bus. At reset, this is a strap pin. For more information, see
Table 15 on page 19
.
Host Bus Request. A host must assert HBR to request control of the DSP’s external bus.
When HBR is asserted in a multiprocessing system, the bus master relinquishes the
bus and asserts HBG once the outstanding transaction is finished.
Host Bus Grant. Acknowledges HBR and indicates that the host can take control of
the external bus. When relinquishing the bus, the master DSP three-states the
ADDR31–0, DATA63–0, MSH, MSSD3–0, MS1–0, RD, WRL, WRH, BMS, BRST, IORD,
IOWR, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM and HDQM pins, and the DSP puts
the SDRAM in self-refresh mode. The DSP asserts HBG until the host deasserts HBR.
In multiprocessor systems, the current bus master DSP drives HBG, and all slave DSPs
monitor it.
Core Priority Access. Asserted while the DSP’s core accesses external memory. This
pin enables a slave DSP to interrupt a master DSP’s background DMA transfers and
gain control of the external bus for core-initiated transactions. CPA is an open drain
output, connected to all DSPs in the system. If not required in the system, leave CPA
unconnected (external pullups will be required for DSP ID=1 through ID=7).
DMA Priority Access. Asserted while a high-priority DSP DMA channel accesses
external memory. This pin enables a high-priority DMA channel on a slave DSP to
interrupt transfers of a normal-priority DMA channel on a master DSP and gain control
of the external bus for DMA-initiated transactions. DPA is an open drain output,
connected to all DSPs in the system. If not required in the system, leave DPA uncon-
nected (external pullups will be required for DSP ID=1 through ID=7).
ID2–0
I (pd)
au
BM
O
au
BOFF
I
epu
BUSLOCK
O/T
(pu_0)
I
au
HBR
epu
HBG
I/O/T
(pu_0)
epu
1
CPA
I/O/OD
(pu_od_0)
epu
DPA
I/O/OD
(pu_od_0)
epu
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
1
This external pull-up resistor may be omitted for the ID=000 TigerSHARC processor.
相關(guān)PDF資料
PDF描述
ADSP-TS203S TigerSHARC Embedded Processor
ADSP-TS203SABP-X TigerSHARC Embedded Processor
ADSP21062 DSP Microcomputer Family
ADT05 Low Voltage, Resistor Programmable Thermostatic Switch(低工作電壓、具有可變電阻的溫度調(diào)節(jié)開關(guān))
ADT45 Low Voltage SOT-23 Temperature Sensors(低壓溫度傳感器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADSP-TS202SABPZ050 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點 接口:I²C，McASP，McBSP 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
ADSP-TS203SABP-050 功能描述:IC DSP FLOAT/FIXED 500MHZ 576BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS203SABP-05X 制造商:Analog Devices 功能描述:
ADSP-TS203SABPZ050 功能描述:IC PROCESSOR 500MHZ 576BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:TigerSHARC® 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤
ADSP-TS203SBBPZ050 制造商:Analog Devices 功能描述:DSP - Bulk
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*