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參數(shù)資料
| 型號： | ADSP-TS202SABP-X |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | TigerSHARC Embedded Processor |
| 中文描述： | 64-BIT, OTHER DSP, PBGA576 |
| 封裝： | 25 X 25 MM, MS-034, EBGA-576 |
| 文件頁數(shù)： | 13/40頁 |
| 文件大小： | 615K |
| 代理商： | ADSP-TS202SABP-X |
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ADSP-TS202S
Preliminary Technical Data
Rev. PrB
|
Page 13 of 40
|
December 2003
Table 5. Pin Definitions—External Port Bus Controls
Signal
ADDR31–0
Type
I/O/T
(pu_ad)
Term
nc
Description
Address Bus. The DSP issues addresses for accessing memory and peripherals on
these pins. In a multiprocessor system, the bus master drives addresses for accessing
internal memory or I/O processor registers of other ADSP-TS202S processors. The DSP
inputs addresses when a host or another DSP accesses its internal memory or I/O
processor registers.
External Data Bus. The DSP drives and receives data and instructions on these pins.
Pullup/down resistors on unused DATA pins are unnecessary.
Memory Read. RD is asserted whenever the DSP reads from any slave in the system,
excluding SDRAM. When the DSP is a slave, RD is an input and indicates read trans-
actions that access its internal memory or universal registers. In a multiprocessor
system, the bus master drives RD. RD changes concurrently with ADDR pins.
Write Low. WRL is asserted in two cases: When the ADSP-TS202S processor writes to
an even address word of external memory or to another external bus agent; and when
the ADSP-TS202S processor writes to a 32-bit zone (host, memory or DSP
programmed to 32-bit bus). An external master (host or DSP) asserts WRL for writing
to a DSP’s low word of internal memory. In a multiprocessor system, the bus master
drives WRL. WRL changes concurrently with ADDR pins. When the DSP is a slave, WRL
is an input and indicates write transactions that access its internal memory or
universal registers.
Write High. WRH is asserted when the ADSP-TS202S processor writes a long word (64
bits) or writes to an odd address word of external memory or to another external bus
agent on a 64-bit data bus. An external master (host or another DSP) must assert WRH
for writing to a DSP’s high word of 64-bit data bus. In a multiprocessing system, the
bus master drives WRH. WRH changes concurrently with ADDR pins. When the DSP
is a slave, WRH is an input and indicates write transactions that access its internal
memory or universal registers.
Acknowledge. External slave devices can de-assert ACK to add wait states to external
memory accesses. ACK is used by I/O devices, memory controllers and other periph-
erals on the data phase. The DSP can de-assert ACK to add wait states to read and
write accesses of its internal memory. The pullup is 50
on low-to-high transactions
and is 500
on all other transactions.
Boot Memory Select. BMS is the chip select for boot EPROM or flash memory. During
reset, the DSP uses BMS as a strap pin (EBOOT) for EPROM boot mode. In a multipro-
cessor system, the DSP bus master drives BMS. For details, see
Reset and Booting on
page 9
and see the EBOOT signal description in
Table 15 on page 19
.
Memory Select. MS0 or MS1 is asserted whenever the DSP accesses memory banks 0
or 1 respectively. MS1–0 are decoded memory address pins that change concurrently
with ADDR pins. When ADDR31:27 = 0b00110, MS0 is asserted. When ADDR31:27 =
0b00111, MS1 is asserted. In multiprocessor systems, the master DSP drives MS1–0.
Memory Select Host. MSH is asserted whenever the DSP accesses the host address
space (ADDR31 = 0b1). MSH is a decoded memory address pin that changes concur-
rently with ADDR pins. In a multiprocessor system, the bus master DSP drives MSH.
Burst. The current bus master (DSP or host) asserts this pin to indicate that it is reading
or writing data associated with consecutive addresses. A slave device can ignore
addresses after the first one and increment an internal address counter after each
transfer. For host-to-DSP burst accesses, the DSP increments the address automati-
cally while BRST is asserted.
DATA63–0
I/O/T
(pu_ad)
I/O/T
(pu_0)
nc
RD
epu
WRL
I/O/T
(pu_0)
epu
WRH
I/O/T
(pu_0)
epu
ACK
I/O/T/OD
(pu_od_0)
epu
BMS
O/T
(pu_0)
au
MS1–0
O/T
(pu_0)
nc
MSH
O/T
(pu_0)
nc
BRST
I/O/T
(pu_0)
epu
I
= input;
A
= asynchronous;
O
= output;
OD
= open drain output;
T
= Three-State;
P
= power supply;
G
= ground;
pd
= internal pulldown 5 k
;
pu
= internal pullup 5 k
;
pd_0
= internal pulldown 5 k
on DSP ID=0;
pu_0
= internal pullup 5 k
on DSP
ID=0;
pu_od_0
= internal pullup 500
on DSP ID=0;
pd_m
= internal pulldown 5 k
on DSP bus master;
pu_m
= internal pullup 5 k
on DSP
bus master;
pu_ad
= internal pullup 40 k
; For more pulldown and pullup information, see
Electrical Characteristics on page 21
.
Term (for termination) column symbols:
epd = External pull-down approximately 5 k
to V
SS
; epu = External pull-up approximately 5 k
to V
DD_IO
, nc = Not connected; au = Always used.
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