參數(shù)資料
型號： ADSP-BF516BBCZ-4F4
廠商： Analog Devices Inc
文件頁數(shù)： 9/68頁
文件大小： 0K
描述： IC DSP 16/32B 400MHZ 168CSPBGA
標準包裝： 1
系列： Blackfin®
類型： 定點
接口： 以太網(wǎng)，I²C，PPI，RSI，SPI，SPORT，UART/USART
時鐘速率： 400MHz
非易失內(nèi)存： 閃存（4Mb）
芯片上RAM： 116kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 168-LFBGA，CSPBGA
供應(yīng)商設(shè)備封裝： 168-CSPBGA（12x12）
包裝： 托盤
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 17 of 68
|
January 2011
SIGNAL DESCRIPTIONS
The processors’ signal definitions are listed in Table 7. In order
to maintain maximum function and reduce package size and
signal count, some signals have dual, multiplexed functions. In
cases where signal function is reconfigurable, the default state is
shown in plain text, while the alternate function is shown in
italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. During hiber-
nate all outputs are three-stated unless otherwise noted in
All I/O signals have their input buffers disabled with the excep-
tion of the signals noted in the data sheet that need pull-ups or
pull downs if unused.
The SDA (serial data) and SCL (serial clock) pins/balls are open
drain and therefore require a pullup resistor. Consult version
2.1 of the I2C specification for the proper resistor value.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D. The termination resistors should
be placed near the processor to reduce transients and improve
signal integrity. The resistance value, typically 33 Ω or 47 Ω,
should be chosen to match the average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Table 7. Signal Descriptions
Signal Name
Type Function
Driver
Type1
EBIU
ADDR19–1
O
Address Bus
A
DATA15–0
I/O
Data Bus
A
ABE1–0/SDQM1–0
O
Byte Enable or Data Mask
A
AMS1–0
O
Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used)
A
ARE
O
Asynchronous Memory Read Enable
A
AWE
O
Asynchronous Memory Write Enable
A
SRAS
O
SDRAM Row Address Strobe
A
SCAS
O
SDRAM Column Address Strobe
A
SWE
OSDRAM Write Enable
A
SCKE
O
SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-refresh
is used)
A
CLKOUT
O
SDRAM Clock Output
B
SA10
O
SDRAM A10 Signal
A
SMS
O
SDRAM Bank Select
A
Port F: GPIO and Multiplexed Peripherals
PF0/ETxD2/PPI D0/SPI1SEL2/TACLK6
I/O
GPIO/Ethernet MII Transmit D2/PPI Data 0/SPI1 Slave Select 2/Timer6 Alternate
Clock
C
PF1/ERxD2/PPI D1/PWM AH/TACLK7
I/O
GPIO/Ethernet MII Receive D2/PPI Data 1/PWM AH Output/Timer7 Alternate Clock C
PF2/ETxD3/PPI D2/PWM AL
I/O
GPIO/Ethernet Transmit D3/PPI Data 2/PWM AL Output
C
PF3/ERxD3/PPI D3/PWM BH/TACLK0
I/O
GPIO/Ethernet MII Data Receive D3/PPI Data 3/PWM BH Output/Timer0 Alternate
Clock
C
PF4/ERxCLK/PPI D4/PWM BL/TACLK1
I/O
GPIO/Ethernet MII Receive Clock/PPI Data 4/PWM BL Out/Timer1 Alternate CLK
C
PF5/ERxDV/PPI D5/PWM CH/TACI0
I/O
GPIO/Ethernet MII Receive Data Valid/PPI Data 5/PWM CH Out
/Timer0 Alternate Capture Input
C
PF6/COL/PPI D6/PWM CL/TACI1
I/O
GPIO/Ethernet MII Collision/PPI Data 6/PWM CL Out/Timer1 Alternate Capture Input C
PF7/SPI0SEL1/PPI D7/PWMSYNC
I/O
GPIO/SPI0 Slave Select 1/PPI Data 7/PWM Sync
C
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