參數(shù)資料
型號： ADSP-BF516BBCZ-4F4
廠商： Analog Devices Inc
文件頁數(shù)： 49/68頁
文件大?。?/td> 0K
描述： IC DSP 16/32B 400MHZ 168CSPBGA
標準包裝： 1
系列： Blackfin®
類型： 定點
接口： 以太網(wǎng)，I²C，PPI，RSI，SPI，SPORT，UART/USART
時鐘速率： 400MHz
非易失內存： 閃存（4Mb）
芯片上RAM： 116kB
電壓 - 輸入/輸出： 1.8V，2.5V，3.3V
電壓 - 核心： 1.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 168-LFBGA，CSPBGA
供應商設備封裝： 168-CSPBGA（12x12）
包裝： 托盤
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. B
|
Page 53 of 68
|
January 2011
Output Disable Time Measurement
Output signals are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay from
their output high or low voltage. The output disable time tDIS is
the difference between tDIS_MEASURED and tDECAY as shown on the
left side of Figure 54.
The time for the voltage on the bus to decay by
ΔV is dependent
on the capacitive load CL and the load current IL. This decay
time can be approximated by the equation:
The time tDECAY is calculated with test loads CL and IL and with
ΔV equal to 0.25 V for VDDEXT/VDDMEM (nominal) = 2.5 V/3.3 V
and 0.15 V for VDDEXT/VDDMEM (nominal) = 1.8 V.
The time tDIS_MEASURED is the interval from when the reference
signal switches to when the output voltage decays
ΔV from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose
ΔV
to be the difference between the ADSP-BF51x processor’s out-
put voltage and the input threshold for the device requiring the
hold time. CL is the total bus capacitance (per data line), and IL is
the total leakage or three-state current (per data line). The hold
time is tDECAY plus the various output disable times as specified
in the Timing Specifications on Page 27 (for example tDSDAT for
an SDRAM write cycle as shown in SDRAM Interface Timing
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 55). VLOAD is equal
to (VDDEXT/VDDMEM)/2. The graphs of Figure 56 through
Figure 67 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
tDIS
tDIS_MEASURED tDECAY
–
=
tDECAY
CL V
Δ
() I
L
=
Figure 55. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 56. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V VDDEXT/VDDMEM)
T1
ZO = 50
: (impedance)
TD = 4.04 ± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50
:
0.5pF
70
:
400
:
45
:
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
VLOAD
DUT
OUTPUT
50
:
6
RISE
AND
F
ALL
TIME
(ns)
LOAD CAPACITANCE (pF)
0
50
100
150
250
12
10
0
2
4
8
200
t
RISE
t
FALL
t
RISE = 1.8V @ 25°C
t
FALL = 1.8V @ 25°C
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