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參數(shù)資料
| 型號(hào)： | ADSP-21MOD970-510 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | Multiport Internet Gateway Processor Data Pump Solution(多端口網(wǎng)關(guān)處理器數(shù)據(jù)泵解決方案) |
| 中文描述： | 56 kbps DATA, 8 kbps FAX, MODEM, PBGA304 |
| 封裝： | PLASTIC, BGA-304 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大小： | 94K |
| 代理商： | ADSP-21MOD970-510 |
REV. 0
ADSP-21mod970-510
–7–
Receive Data Buffer Read
The receive buffer is a circular buffer in the internal memory of
the modem processor. The controller reads from this buffer and
updates the read pointer, while the modem writes to this buffer
and updates the write pointer.
Entries 6–11 in the FifoDB_ table represent the receive data
buffer. The four values used by the controller are:
Table XI. FifoDB_ Table Description
FifoDB_ Entries
Description
FifoDB_+6
FifoDB_+7
FifoDB_+10
FifoDB_+11
Receive FIFO Length
Receive FIFO Read Pointer
Receive FIFO Write Pointer
Receive FIFO Buffer Address
The controller must first read the control word FIFO so that the
receive buffer can determine how many bytes need to be read.
The controller adds the value of the address represented by the
symbol EC_Rx_Fifo to the offset value represented by the
symbol Rx_read_idx. This resulting address is used to read the
FIFO control word. The format for this 16-bit control word is
as follows:
Table XII. Bit Definitions
Bits
Definition
Bit [12]
Bit [11]
End of Frame Flag (1 = End of Frame)
Voice Activity Detection Flag
0
Silence Frame
1
Voice Frame
Mode (V.14, HDLC)
00
V.14 Asynchronous Communications Mode
10
HDLC/V.42 Mode
01
Raw Mode (Pure Bitstream)
11
Modified V.14 (With Multiple Stop Bits)
Length of Frame in Bytes
Bits [10:9]
Bits [8:0]
The controller needs to update the receive read pointer in the
FifoDB_ and the Rx_read_idx in the Control Word FIFO when
it has finished reading in the data.
The receive data FIFO is implemented as a circular buffer. The
read pointer, length value, and buffer address entries in the
FifoDB_ are used by the controller to calculate when the data
wraps around in the buffer.
TELEMETRY FIFO
A real time data acquisition mechanism has been built into the
data pump, which is designed to simplify the debugging process.
This mechanism involves the use of FIFO to collect statistics on
modem operations while the modem is running. This FIFO is
called the telemetry FIFO.
When the modem software is built by Analog Devices at the
factory, a set of statistics is called out to be collected periodi-
cally. This can be changed by Analog Devices and used as a
debugging tool. If the user includes the capability to collect data
from the telemetry FIFO in the controller, the design will be
easier to debug.
DATA MANAGEMENT FUNCTIONS
The ADSP-21mod970-510 enables users to monitor modem
data management functions, including the following:
Channel Round Trip Delay Estimate in either milliseconds or
samples.
Information regarding what modulation is currently active
(V8, V.22, V.32, V.34, K56Flex, V.90).
Call progress status (not connected data mode, rate renego-
tiation, retrain)
Equalizer mean square error estimation as a measure of re-
ceived signal quality.
Digital pad information (V.90 and K56Flex).
Robbed bit signaling (RBS) frame information.
Current transmit and receive data rates.
Input and output level.
SERIAL PORTS
The ADSP-21mod970 processor incorporates two complete
synchronous, double-buffered serial ports for serial communica-
tions. The serial ports interface directly to a time-division multi-
plexed (TDM) 1544 kbps (T1) or 2048 kbps (E1) serial stream,
to an 8K sample/s data stream, or to an 8-bit companded (64 kb/s)
data stream (DS0). The serial ports operate under modem soft-
ware control.
Serial Telco PCM TDM Data Stream Architecture
The serial Telco PCM TDM data stream architecture, shown in
Figure 5, is the most common architecture. In this architecture,
the data pump pool may have a local Telco interface that pro-
vides a serial TDM data stream of Telco PCM data to the DSP
through the DSP’s Serial Port. Up to 24/32 DSPs can be con-
nected, through the Serial Port, to a 24/32 channel serial TDM
data stream.
NOTE: The Controller and Host can be configured in either a single machine, as shown in Figure 5, or two separate ones.
ADSP-21mod970
TELCO PCM
I/F
HOST
MEMORY I/F
DMA
PORT
SERIAL
PORT
CONTROLLER
ADSP-21mod970
ADSP-21mod970
ADSP-21mod970
Figure 5. Serial Telco PCM TDM Data Stream Architecture
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