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參數(shù)資料
| 型號： | ADSP-21MOD970-510 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調制器/解調器 |
| 英文描述： | Multiport Internet Gateway Processor Data Pump Solution(多端口網(wǎng)關處理器數(shù)據(jù)泵解決方案) |
| 中文描述： | 56 kbps DATA, 8 kbps FAX, MODEM, PBGA304 |
| 封裝： | PLASTIC, BGA-304 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 94K |
| 代理商： | ADSP-21MOD970-510 |
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ADSP-21mod970-510
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DATA FIFO ACCESS
The modem has two general sets of FIFOs that support com-
munications between the modem and the controller. The first
set are the data FIFOs, which hold the actual data that has been
received or is to be sent by the modem. The second set contains
control word FIFOs. Control word FIFOs used to communi-
cate information such as number of bytes transferred and the
mode used to transfer data, for example V.14 or HDLC.
All FIFOs are accessed with the use of pointers. A
read pointer
is
used when information needs to be
read from
the FIFO and a
write pointer
is used when information is to be
written into
the
FIFO. After the read or write operation is completed, the pointer
must be updated. The read pointer should always point to the
location containing the next value to be read. The write pointer
should always point to the next empty location to be written.
When the read pointer and the write pointer point to the same
location (read pointer = write pointer), the FIFO is considered
to be empty.
Since the data FIFOs are implemented as circular buffers, the
controller must make sure that when it updates the read pointer
and the write pointer, it appropriately wraps the pointer back
around to the start of the buffer when the bottom of the buffer is
reached. This can be accomplished by checking the number of
locations remaining until the end of the buffer. If the number of
transfers is less than this value, all words can be transferred as
one block without worrying about address wraparound. If the
number of transfers is larger, then the controller will need to
break up the transfer into two blocks. The first transfer will go
until the end of the buffer is reached. The buffer will then reset
the pointer to the start of the buffer to start a new DMA transfer
and transfer the second block.
Data FIFOs
There are two data FIFOs used for communication between the
controller and the modem. One FIFO is used for data that is to
be
transmitted
by the modem. The controller writes data into
this FIFO and the modem reads data
from
this FIFO. A second
FIFO is used for data that has been
received
by the modem. The
modem writes data into this FIFO and the controller reads data
from this FIFO. The read pointer for the data FIFO is only
updated by the component, either controller or modem, that
reads from the FIFO. The write pointer is updated with the
same rule.
Data Format
The FIFOs reside in the internal data memory of the modem
processor and are 16 bits wide. Two bytes are packed into each
FIFO location. Bytes are loaded into the FIFO in the high byte
position first, followed by the low byte position. Also, each byte
is written in a bit-reversed fashion. For example, the data word
0x ABCD must first be byte-swapped so that the first byte is in
the high byte position (CD AB = 11001101 10101011). Then,
each byte is bit reversed (10110011 11010101 = B3 D5). If an
odd number of bytes is used, the high byte position will hold the
last byte and the lower byte position will hold an undefined
value. All operations on FIFOs process a full word (16 bits) of
data at a time.
FIFO Table
The data FIFOs are accessed by the controller using four pieces
of information:
The FIFO Starting Address
The Write Pointer Value, Offset into the FIFO
The Read Pointer Value, Offset into the FIFO
The FIFO length
This information is contained in a table. The table is symboli-
cally referenced with the symbol *-_. The symbol table provided
with the modem software specifies the actual memory address of
FifoDB_. The first 12 locations of the FifoDB_ table contain
information about the transmit buffer (first six locations of
table) and the receive buffer (next six locations of table).
Table V. FifoDB_ Table
Buffer
Location
Transmit Buffer FIFO Information
Locations 0–5 of the
FifoDB Structure
Locations 6–11 of the
FifoDB Structure
Receive Buffer FIFO information
The six values in the FifoDB table are shown below. Only four
of the six locations are used by the controller:
Length in Words
Read Word Pointer
Read Bit Pointer
Write Word Pointer
Write Bit Pointer
FIFO Base Address
Control Word FIFOs
Two control word FIFOs are used to hold information about
the data FIFO transfers. Control word FIFOs are circular buff-
ers nine locations long, which will hold the most recent nine
control words. The control word is a 16-bit value with the bit
field definitions listed on Table VI:
Table VI. Control Word FIFOs Bit Definitions
Bits
Definition
Bit [13:12]
Control Word Type (Partial Frame, End of Frame,
Abort)
00
Partial Frame
01
End of Frame
10
Abort from Peer Modem
11
Abort from DSP, Due to Bad CRC or
No Data FIFO Space Available
Reserved
Set to 0
Mode (V.14, HDLC)
00
V.14 Asynchronous Communications
Mode
01
HDLC/V.42 Mode
10
Raw Mode (Pure Bitstream)
11
Modified V.14 (With Multiple Stop Bits)
Length of Frame in Bytes
Bit [11]
Bits [10:9]
Bits [8:0]
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