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參數(shù)資料
| 型號： | ADSP-21MOD970-510 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 調(diào)制器/解調(diào)器 |
| 英文描述： | Multiport Internet Gateway Processor Data Pump Solution(多端口網(wǎng)關(guān)處理器數(shù)據(jù)泵解決方案) |
| 中文描述： | 56 kbps DATA, 8 kbps FAX, MODEM, PBGA304 |
| 封裝： | PLASTIC, BGA-304 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 94K |
| 代理商： | ADSP-21MOD970-510 |
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ADSP-21mod970-510
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When the controller reads data from the receive data FIFO in
V.42 mode, the last two bytes will be a 16-bit CRC value and
can be ignored by the controller. The CRC bytes need to be
read by the controller, but the actual values can be ignored. It is
important for the controller to read in these bytes in order to
maintain the read and write pointers of the data FIFO.
The control word FIFOs are accessed with the use of a read
pointer and a write pointer. There are three pieces of informa-
tion about each of the two control word FIFOs:
FIFO Starting Address
Read Pointer Value
Write Pointer Value
These pieces of information are stored in locations of the mo-
dem processor’s internal data memory. The address values are
referenced symbolically. The symbol table supplied with the
modem software can be used to find the absolute addresses of
these memory locations. The symbols are as follows.
Table VII. Control Word FIFO for Transmit Data
FIFO Name
Description
EC_Tx_Fifo
Base address of the control word FIFO for
data from the controller to the modem.
Address of the read index for the transmit
control word FIFO.
Address of the write index for the transmit
control word FIFO.
Tx_read_idx
Tx_write_idx
Table VIII. Control Word FIFO for Receive Data
FIFO Name
Description
EC_Rx_Fifo
Base address of the control word FIFO for
data from the modem to the controller.
Address of the read index for the receive
control word FIFO.
Address of the write index for the receive
control word FIFO.
Rx_read_idx
Rx_write_idx
After the controller completes a buffer write to the transmit data
FIFO it must update the transmit control word FIFO with in-
formation about the transfer. This includes the number of
bytes written to the data buffer, the mode, and information
about whether or not the buffer represents the end of a frame.
The modem can then read the control word to obtain informa-
tion about the transfer. The controller must write the data into
the data FIFO before it writes to the control FIFO.
Before the controller begins a buffer read from the receive data
FIFO, it must read the receive control word FIFO to get infor-
mation about the transfer. This includes the number of bytes
available to be read from the data buffer, the mode and informa-
tion about whether or not the buffer represented the end of a
frame. The modem will have written these values into the con-
trol word FIFO after it wrote the received data values into the
receive data buffer. The controller must read the control FIFO
before reading the data FIFO.
Control Word Versus Data FIFOs
Control word FIFOs do not use the FifoDB_ structure. Instead,
the control word FIFOs are directly indexed by the symbol
name. Control Word Fifos use an index instead of a pointer to
access the control words contained in the FIFO.
Overall Data Buffer Read/Write Process
The controller should use the following processes to write or
read data:
Transmit Data Buffer Write
Receive Data Buffer Read
Transmit Data Buffer Write
The transmit buffer is a circular buffer in the internal memory
of the modem processor. The controller writes to this buffer and
updates the write pointer while the modem reads from this
buffer and updates the read pointer.
Entries 0-5 in the FifoDB_ table represent the transmit data
buffer. The four values used by the controller are:
Table IX. FifoDB_ Table Description
FifoDB_ Entries
Description
FifoDB_+0
FifoDB_+1
FifoDB_+3
FifoDB_+5
Transmit FIFO Length
Transmit FIFO Read Pointer
Transmit FIFO Write Pointer
Transmit FIFO Buffer Address
The controller uses the read pointer, write pointer, and length
value to determine if there is space in the FIFO. The controller
updates the write pointer once it has finished adding data to the
FIFO.
The transmit data FIFO is implemented as a circular buffer.
The controller needs to calculate if the data transfer is going to
cause the FIFO to wrap around and adjust the write pointer
accordingly.
The controller also needs to update the control word FIFO. The
controller updates the control word FIFO by writing a control
word to the address calculated by adding the address repre-
sented by the symbol EC_Tx_Fifo plus the offset value repre-
sented by the symbol Tx_write_idx.
Table X. Bit Definitions
Bits
Definition
Bit [13]
Bit [12]
Bit [11]
Abort Indication (1 = Abort)
End of Frame Indication (1 = End of Frame)
Reserved
Set to 0
Bits [10:9] Mode (V.14, HDLC)
00
V.14 Asynchronous Communications Mode
10
HDLC/V.42 Mode
01
Raw Mode (Pure Bitstream)
11
Modified V.14 (With Multiple Stop Bits)
Bits [8:0]
Length of Frame in Bytes
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