Data Memory, Host Mode allows access to all internal memory. External overlay access is limited by a single external addr" />
參數(shù)資料
型號(hào)： ADSP-2189MKCAZ-300
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/32頁(yè)
文件大?。?/td> 0K
描述： IC DSP CONTROLLER 16BIT 144-MBGA
標(biāo)準(zhǔn)包裝： 1
系列： ADSP-21xx
類型： 定點(diǎn)
接口： 主機(jī)接口，串行端口
時(shí)鐘速率： 75MHz
非易失內(nèi)存： 外部
芯片上RAM： 192kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 2.50V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 144-LFBGA
供應(yīng)商設(shè)備封裝： 144-迷你型BGA
包裝： 托盤(pán)
REV. A
ADSP-2189M
–9–
Data Memory, Host Mode allows access to all internal
memory. External overlay access is limited by a single external
address line (A0).
Table IV. DMOVLAY Bits
PMOVLAY
Memory
A13
A12:0
0, 4, 5, 6, 7
Internal
Not Applicable Not Applicable
1
External
0
13 LSBs of Address
Overlay 1
Between 0x2000
and 0x3FFF
2
External
1
13 LSBs of Address
Overlay 2
Between 0x2000
and 0x3FFF
Memory Mapped Registers (New to the ADSP-2189M)
The ADSP-2189M has three memory mapped registers that
differ from other ADSP-21xx Family DSPs. The slight modifi-
cations to these registers (Wait-State Control, Programmable
Flag and Composite Select Control and System Control) pro-
vide the ADSP-2189M’s wait-state and
BMS control features.
DWAIT
IOWAIT3
IOWAIT2
IOWAIT1
IOWAIT0
DM(0x3FFE)
WAIT STATE MODE SELECT (ADSP-2189M)
0 = NORMAL MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 7)
1 = 2N+1 MODE (DWAIT, IOWAIT0-3 = N WAIT STATES, RANGING FROM 0 TO 15)
WAIT-STATE CONTROL
11
1
11
111
1
15 14 13 12 11 10
9
8
7
6
5
43210
Figure 6. Wait-State Control Register (ADSP-2189M)
BMWAIT
(BIT-15, ADSP-2189M)
CMSSEL
0 = DISABLE CMS
1 = ENABLE CMS
DM(0x3FE6)
PROGRAMMABLE FLAG & COMPOSITE SELECT CONTROL
PFTYPE
0 = INPUT
1 = OUTPUT
(WHERE BIT: 11-IOM, 10BM, 9-DM, 8-PM)
11
1
11
111
1
15 14 13 12 11 10
9
8
7
6
5
43210
Figure 7. Programmable Flag and Composite Select Con-
trol Register
RESERVED, ALWAYS = 0
(ADSP-2189M)
SPORT0 ENABLE
0 = DISABLE
1 = ENABLE
DM(0x3FFF)
SYSTEM CONTROL
SPORT1 ENABLE
0 = DISABLE
1 = ENABLE
SPORT1 CONFIGURE
0 = FI, FO,
IRQ0, IRQ1, SCLK
1 = SPORT1
DISABLE
BMS (ADSP-2189M)
0 = ENABLE
BMS
1 = DISABLE
BMS, EXCEPT WHEN MEMORY
STROBES ARE THREE-STATED
PWAIT
PROGRAM MEMORY
WAIT STATES
00
0
1
00
000
0
1
15 14 13 12 11 10
9
8
7
6
5
43210
Figure 8. System Control Register
I/O Space (Full Memory Mode)
The ADSP-2189M supports an additional external memory
space called I/O space. This space is designed to support simple
connections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit-wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated three-bit wait-state
registers, IOWAIT0–3, which, in combination with the wait-
state mode bit, specify up to 15 wait-states to be automatically
generated for each of four regions. The wait-states act on ad-
dress ranges as shown in Table V.
Table V. Wait-States
Address Range
Wait-State Register
0x000–0x1FF
IOWAIT0 and Wait-State Mode Select Bit
0x200–0x3FF
IOWAIT1 and Wait-State Mode Select Bit
0x400–0x5FF
IOWAIT2 and Wait-State Mode Select Bit
0x600–0x7FF
IOWAIT3 and Wait-State Mode Select Bit
Composite Memory Select (
CMS)
The ADSP-2189M has a programmable memory select signal
that is useful for generating memory select signals for memories
mapped to more than one space. The
CMS signal is generated
to have the same timing as each of the individual memory
select signals (
PMS, DMS, BMS, IOMS) but can combine
their functionality.
When set, each bit in the CMSSEL register causes the
CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the
PMS and DMS bits in the
CMSSEL register and use the
CMS pin to drive the chip select
of the memory, and use either
DMS or PMS as the additional
address bit.
The
CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the
BMS bit.
Byte Memory Select (
BMS)
The ADSP-2189M’s
BMS disable feature combined with the
CMS pin lets you use multiple memories in the byte memory
space. For example, an EPROM could be attached to the
BMS
select, and an SRAM could be connected to
CMS. Because
BMS is enabled at reset, the EPROM would be used for boot-
ing. After booting, software could disable
BMS and set the
CMS signal to respond to BMS, enabling the SRAM.
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