- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19396 > ADSP-2186MKCAZ-300 (Analog Devices Inc)IC DSP CONTROLLER 16BIT 144MBGA PDF資料下載
參數(shù)資料
| 型號： | ADSP-2186MKCAZ-300 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144MBGA |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，串行端口 |
| 時鐘速率： | 75MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 144-迷你型BGA |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁當(dāng)前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
REV. 0
–14–
ADSP-2186M
Table V. Wait States
Address Range
Wait State Register
0x000–0x1FF
IOWAIT0 and Wait State Mode Select Bit
0x200–0x3FF
IOWAIT1 and Wait State Mode Select Bit
0x400–0x5FF
IOWAIT2 and Wait State Mode Select Bit
0x600–0x7FF
IOWAIT3 and Wait State Mode Select Bit
Composite Memory Select (
CMS)
The ADSP-2186M has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The
CMS signal is gener-
ated to have the same timing as each of the individual memory
select signals (
PMS, DMS, BMS, IOMS) but can combine their
functionality.
Each bit in the CMSSEL register, when set, causes the
CMS
signal to be asserted when the selected memory select is
asserted. For example, to use a 32K word memory to act as both
program and data memory, set the
PMS and DMS bits in the
CMSSEL register and use the
CMS pin to drive the chip
select of the memory, and use either
DMS or PMS as the
additional address bit.
The
CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the
CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at reset,
except the
BMS bit.
Byte Memory Select (
BMS)
The ADSP-2186M’s
BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the
BMS
select, and an SRAM could be connected to
CMS. Because at
reset
BMS is enabled, the EPROM would be used for booting.
After booting, software could disable
BMS and set the CMS
signal to respond to
BMS, enabling the SRAM.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space con-
sists of 256 pages, each of which is 16K
× 8.
The byte memory space on the ADSP-2186M supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses data
bits 23:16 and address bits 13:0 to create a 22-bit address. This
allows up to a 4 meg
× 8 (32 megabit) ROM or RAM to be used
without glue logic. All byte memory accesses are timed by the
BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space. The
BDMA circuit is able to access the byte memory space while the
processor is operating normally and steals only one DSP cycle
per 8-, 16- or 24-bit word transferred.
BDMA CONTROL
BMPAGE
BTYPE
BDIR
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
00
0
00
000
0
1
0
15 14 13 12 11 10
9
8
7
6
5
43210
DM (0x3FE3)
BDMA
OVERLAY
BITS*
THESE BITS SHOULD ALWAYS
BE WRITTEN WITH ZEROS.
*
Figure 9. BDMA Control Register
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table VI shows the data formats sup-
ported by the BDMA circuit.
Table VI. Data Formats
BTYPE
Internal Memory Space Word Size Alignment
00
Program Memory
24
Full Word
01
Data Memory
16
Full Word
10
Data Memory
8
MSBs
11
Data Memory
8
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally, the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches zero,
the transfers have finished and a BDMA interrupt is generated.
The BMPAGE and BEAD registers must not be accessed by the
DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with wait
states set by BMWAIT. These accesses continue until the count
reaches zero. When enough accesses have occurred to create a
destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor, and start execution at address 0 when
the BDMA accesses have completed.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GBA24DRMD | CONN EDGECARD 48POS .125 SQ WW |
| GSM44DRTF | CONN EDGECARD 88POS DIP .156 SLD |
| ADSP-2184LBSTZ-160 | IC DSP CONTROLLER 16BIT 100LQFP |
| GMM44DRTF | CONN EDGECARD 88POS DIP .156 SLD |
| ECM12DSEN | CONN EDGECARD 24POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-2186MKST-300 | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 75MHz 75MIPS 100-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:75 MHZ 16-BIT DSP,2.5V,8K/8K 2.5V,LQFP - Bulk 制造商:Analog Devices 功能描述:DIGITAL SIGNAL PROCESSOR IC ((NW)) |
| ADSP-2186MKST-300R | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 75MHz 75MIPS 100-Pin LQFP T/R |
| ADSP-2186MKSTZ-300 | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-2186MKSTZ300R | 功能描述:IC DSP CONTROLLER 16BIT 100LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-2186N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ADSP-2184N-ADSP-2189N: DSP Microcomputer Data Sheet (Rev. 0. 10/01) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。