參數(shù)資料
型號： ADSP-2186LBSTZ-160
廠商： Analog Devices Inc
文件頁數(shù)： 7/48頁
文件大小： 0K
描述： IC DSP CONTROLLER 16BIT 100LQFP
標準包裝： 1
系列： ADSP-21xx
類型： 定點
接口： 主機接口，串行端口
時鐘速率： 40MHz
非易失內(nèi)存： 外部
芯片上RAM： 40kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 3.30V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 托盤
ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C
|
Page 15 of 48
|
January 2008
Complete assembly and disassembly of instructions
C source-level debugging
Designing an EZ-ICE-Compatible System
ADSP-218xL series members have on-chip emulation support
and an ICE-Port, a special set of pins that interface to the
EZ-ICE. These features allow in-circuit emulation without
replacing the target system processor by using only a 14-pin
connection from the target system to the EZ-ICE. Target sys-
tems must have a 14-pin connector to accept the EZ-ICE’s in-
circuit probe, a 14-pin plug.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If a passive method of maintaining mode information
is being used (as discussed in Setting Memory Mode on Page 4),
it does not matter that the mode information is latched by an
emulator reset. However, if the RESET pin is being used as a
method of setting the value of the mode pins, the effects of an
emulator reset must be taken into consideration.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 13. This circuit forces the value located on the Mode A
pin to logic high, regardless of whether it is latched via the
RESET or ERESET pin.
The ICE-Port interface consists of the following ADSP-218xL
pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and
ELOUT.
These ADSP-218xL pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the
ADSP-218xL and the connector must be kept as short as possi-
ble, no longer than 3 inches.
The following pins are also used by the EZ-ICE: BR, BG, RESET,
and GND.
The EZ-ICE uses the EE (emulator enable) signal to take control
of the ADSP-218xL in the target system. This causes the proces-
sor to use its ERESET, EBR, and EBG pins instead of the RESET,
BR, and BG pins. The BG output is three-stated. These signals
do not need to be jumper-isolated in the system.
The EZ-ICE connects to the target system via a ribbon cable and
a 14-pin female plug. The female plug is plugged onto the 14-
pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 14. This connector must be added to the target board
design to use the EZ-ICE. Be sure to allow enough room in the
system to fit the EZ-ICE probe onto the 14-pin connector.
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—Pin 7 must be removed from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1
0.1 inch. The pin strip header must have at least
0.15 inch clearance on all sides to accept the EZ-ICE probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
Target Memory Interface
For the target system to be compatible with the EZ-ICE emula-
tor, it must comply with the following memory interface
guidelines:
Design the Program Memory (PM), Data Memory (DM), Byte
Memory (BM), I/O Memory (IOM), and Composite Memory
(CM) external interfaces to comply with worst-case device
timing requirements and switching characteristics as specified
in this data sheet. The performance of the EZ-ICE may
approach published worst-case specification for some memory
access timing requirements and switching characteristics.
Note:
If the target does not meet the worst-case chip specifica-
tion for memory access parameters, the circuitry may not be
able to be emulated at the desired CLKIN frequency. Depending
on the severity of the specification violation, the system may be
difficult to manufacture, as DSP components statistically vary in
switching characteristic and timing requirements, within pub-
lished limits.
Restriction:
All memory strobe signals on the ADSP-218xL
(RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
Figure 13. Mode A Pin/EZ-ICE Circuit
PROGRAMMABLE I/O
MODE A/PF0
RESET
ERESET
ADSP-218xL
1k
Figure 14. Target Board Connector for EZ-ICE
1
2
3
4
56
7
8
910
11
12
13
14
GND
KEY (NO PIN)
RESET
BR
BG
TOP VIEW
EBG
EBR
ELOUT
EE
EINT
ELIN
ECLK
EMS
ERESET
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