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| 型號： | ADSP-2186LBSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 100LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，串行端口 |
| 時(shí)鐘速率： | 40MHz |
| 非易失內(nèi)存： | 外部 |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 3.30V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
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ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L
Rev. C
|
Page 13 of 48
|
January 2008
Note: In Full Memory Mode, all locations of 4M-byte memory
space are directly addressable. In Host Memory Mode, only
address pin A0 is available, requiring additional external logic to
provide address information for the byte.
Bootstrap Loading (Booting)
ADSP-218xL series members have two mechanisms to allow
automatic loading of the internal program memory after reset.
The method for booting is controlled by the Mode A, Mode B,
and Mode C configuration bits.
When the mode pins specify BDMA booting, the ADSP-218xL
initiates a BDMA boot sequence when reset is released.
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is set
to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
The ADSP-2100 Family development software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space-compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the
addresses to boot memory must be constructed externally to the
ADSP-218xL. The only memory address bit provided by the
processor is A0.
IDMA Port Booting
ADSP-218xL series members can also boot programs through
its internal DMA port. If Mode C = 1, Mode B = 0, and Mode A
= 1, the ADSP-218xL boots from the IDMA port. IDMA feature
can load as much on-chip memory as desired. Program execu-
tion is held off until the host writes to on-chip program memory
location 0.
BUS REQUEST AND BUS GRANT
ADSP-218xL series members can relinquish control of the data
and address buses to an external device. When the external
device requires access to memory, it asserts the Bus Request
(BR) signal. If the ADSP-218xL is not performing an external
memory access, it responds to the active BR input in the follow-
ing processor cycle by:
Three-stating the data and address buses and the PMS,
DMS, BMS, CMS, IOMS, RD, WR output drivers,
Asserting the bus grant (BG) signal, and
Halting program execution.
If Go Mode is enabled, the ADSP-218xL will not halt program
execution until it encounters an instruction that requires an
external memory access.
If an ADSP-218xL series member is performing an external
memory access when the external device asserts the BR signal, it
will not three-state the memory interfaces nor assert the BG sig-
nal until the processor cycle after the access completes. The
instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory
accesses, the bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers, and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active.
The BGH pin is asserted when an ADSP-218xL series member
requires the external bus for a memory or BDMA access, but is
stopped. The other device can release the bus by deasserting bus
request. Once the bus is released, the ADSP-218xL deasserts BG
and BGH and executes the external memory access.
FLAG I/O PINS
ADSP-218xL series members have eight general-purpose pro-
grammable input/output flag pins. They are controlled by two
memory-mapped registers. The PFTYPE register determines
the direction, 1 = output and 0 = input. The PFDATA register is
used to read and write the values on the pins. Data being read
from a pin configured as an input is synchronized to the
ADSP-218xL’s clock. Bits that are programmed as outputs
will read the value being output. The PF pins default to input
during reset.
In addition to the programmable flags, ADSP-218xL series
members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2.
FL0 to FL2 are dedicated output flags. FI and FO are available as
an alternate configuration of SPORT1.
Note: Pins PF0, PF1, PF2, and PF3 are also used for device con-
figuration during reset.
Figure 12. IDMA OVLAY/Control Registers
ID M A O V E R LA Y
DM (0 x3 FE 7)
RE SE RV ED S E T TO 0
IDDM O V LAY
IDP M O V LAY
00
0
00
0
00
0
00
0
15 14 1 3 12
11 10
9
8
7
6
5
4
3
2
1
0
SH O R T R E A D
ON LY
0 = DIS ABLE
1 = E NABLE
IDM A C O NTRO L (U = U ND E FINE D AT RE S E T)
DM (0 x3 FE 0)
IDM A A ADDRESS
U
UU
UUU
U
UU
U
UU
U
15 14 13 1 2 11
1 0
9
8
7
6
5
4
3
2
1
0
IDM AD DES TINAT IO N M EM O RY
TY PE
0= P M
1= D M
NO TE: RES E RV ED BITS ARE S HO W N O N A G RAY F IE LD. T HES E
BITS SHOULD AL W AYS BE W RITTE N W ITH ZE RO S .
0
RE SE RV ED S E T TO 0
0
RE SE RV ED S E T TO 0
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